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ASIC RTL Design Lead Engineer

Noida

SynthesisRTL DesignASICVerilogSystem Verilog+3

Posted 2 weeks ago

Posted 2 weeks ago

Tessolve - Manager - RTL Design

Bangalore

SynthesisRTL DesignASICSoCVerilogSystem VerilogAMBA+5+2

Posted 1 week ago

Posted 1 week ago

Senior RTL Design Engineer

Bangalore

SynthesisRTL DesignVerilogSystem VerilogTiming ClosureASIC+4+1

Posted 1 week ago

Posted 1 week ago

Tessolve - Lead RTL Design Engineer

Bangalore/Chennai/Hyderabad

SynthesisRTL DesignVerilogSystem VerilogSoC+3

Posted 3 weeks ago

Posted 3 weeks ago

ASIC Engineer - DFT/Synthesis

Bangalore

SynthesisASICDFTStatic Timing AnalysisSoC+3

Posted 1 month ago

Posted 1 month ago

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Staff Engineer - Static Timing Analysis

Bangalore/Greater Noida

SynthesisStatic Timing AnalysisRTLDFTPhysical Design+3

Posted 1 month ago

Posted 1 month ago

Qualcomm Technologies - CPU Physical Design Engineer

Hyderabad

SynthesisPhysical DesignASICSoCPhysical VerificationPrimetimeVerilogC+++6+3

Posted 1 month ago

Posted 1 month ago

Lead RTL Engineer - System Verilog

Bangalore

SynthesisRTLRTL DesignSystem VerilogTiming Closure+3

Posted 1 month ago

Posted 1 month ago

Senior Physical Design Engineer

Bangalore/Chennai

SynthesisPhysical DesignStatic Timing AnalysisFloor PlanningPrimetimePhysical Verification+4+1

Posted 1 month ago

Posted 1 month ago

Senior Engineer/FPGA Design Engineer

Chennai

SynthesisFPGA DesignRTL DesignVHDLVerilogStatic Timing AnalysisSERDES+5+2

Posted 2 months ago

Posted 2 months ago

FPGA Design Engineer - VHDL/Verilog

Hyderabad

SynthesisFPGAVHDLVerilogSystem VerilogRTL DesignFPGA Design+5+2

Posted 2 months ago

Posted 2 months ago

STA & Synthesis Engineer

Malaysia

SynthesisStatic Timing AnalysisRTLDFTPhysical Design+3

Posted 2 months ago

Posted 2 months ago

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Physical Design Engineer - Static Timing Analysis

Hyderabad/Pune

SynthesisPhysical DesignFloor PlanningStatic Timing AnalysisVLSITiming ClosureASIC+5+2

Posted 2 months ago

Posted 2 months ago

Principal CAD Engineer

Hyderabad/Bangalore

SynthesisCADRTLHPCEDA+3

Posted 2 months ago

Posted 2 months ago

DFT Engineer - ATPG

Bangalore

SynthesisASICDFTATPG+2

Posted 3 months ago

Posted 3 months ago

Ambient Scientific - RTL Design Lead/Manager

Bangalore

SynthesisRTLSystem VerilogSoCVerilog+3

Posted 3 months ago

Posted 3 months ago

Sykatiya Technologies - RTL Synthesis Engineer/Senior Engineer

Bangalore

Diversity Inclusive

SynthesisRTLRTL DesignStatic Timing AnalysisSynopsysTCLPhysical Design+5+2

Posted 3 months ago

Posted 3 months ago

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