Static Timing Analysis Jobs

Sykatiya Technologies - Physical Design Engineer - Static Timing Analysis

3 - 15 yrs

5-45 LPA

Bangalore

Static Timing Analysis

Static Timing AnalysisDFTATPGMBIST+2

Makonis software Solutions - DFT Staff Engineer

8 - 12 yrs

Bangalore/Hyderabad

Static Timing AnalysisTiming Closure

STA Engineer - ASIC/SoC Design

4 - 10 yrs

Bangalore

Static Timing AnalysisASICSoCPrimetimeRTLPhysical DesignDFT+5+2

ASIC STA Engineer

6 - 11 yrs

Bangalore

Static Timing AnalysisPhysical DesignRTLFloor PlanningDFT+3

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Mirafra Technologies - Physical Design Engineer

5 - 10 yrs

Bangalore

Static Timing AnalysisDFTATPGMBISTLBIST+3

DFT Architect

10 - 15 yrs

Bangalore/Hyderabad/Ahmedabad

Static Timing AnalysisDFTMBISTSoCATPGRTLPhysical Design+5+2

Lead DFT Engineer - MBIST/SoC

10 - 12 yrs

Bangalore

Static Timing AnalysisSoCDFTEDAPrimetime+3

Leadsoc Technologies - Lead STA Engineer

5 - 12 yrs

Bangalore

Static Timing AnalysisSynthesisPrimetimeRTLDFT+3

Leadsoc Technologies - Lead Synthesis Engineer

5 - 12 yrs

Bangalore

Static Timing AnalysisRTLRTL Design+1

Hardware Engineer - RTL/GDS/STA

3 - 6 yrs

Multiple Locations

Static Timing AnalysisHardware DesignHardware ArchitectureHardware ImplementationPython+3

Hardware Design Engineer II - Static Timing Analysis

3 - 6 yrs

Bangalore

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Hardware Engineer - ASIC/SoC Physical Design

10 - 15 yrs

Bangalore/Hyderabad

Static Timing AnalysisASICSoCPhysical DesignHardware Design+3

Static Timing AnalysisPythonTCLPnR+2

STA Methodology Engineer - Silicon Timing

5 - 7 yrs

Bangalore

Static Timing AnalysisIC DesignPhysical DesignSoC+2

Silicon Labs - Lead Engineer - IC Design

8 - 10 yrs

Hyderabad

Static Timing AnalysisFPGAFPGA DesignHDMIEthernet Port+3

Happiest Minds Technologies - Senior Engineer - FPGA Design

3 - 5 yrs

Others

Static Timing AnalysisRTL DesignVHDLVerilogFPGAFloor Planning+4+1

SensoVision - RTL Design Engineer - VHDL/Verilog

5 - 10 yrs

Mumbai

Posted 4 months ago

Sykatiya Technologies - FPGA Design Engineer - VHDL/Verilog

7 - 8 yrs

Bangalore

Static Timing AnalysisFPGA DesignVerilogVHDLClock Domain Crossing+3

Static Timing AnalysisASICDFTSynthesisSoC+3

ASIC Engineer - DFT/Synthesis

5 - 7 yrs

17-30 LPA

Bangalore

Static Timing AnalysisDFTASICSoCMBISTPhysical DesignVerificationSystem Verilog+6+3

DFT Engineer - Physical Design

5 - 7 yrs

Noida/Pune/Bangalore