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Synopsys - Director - ASIC/RTL Design
Hyderabad
VeriFast Technologies - Physical Design Engineer - ASIC/SoC
Ahmedabad
Modernize Chip Solutions - DFT Engineer
Bangalore
Infineon - Principal Engineer - Physical Design
Static Timing Analysis Lead
Bangalore/Hyderabad
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Architect/Lead - SoC Design Verification
Architect/Lead - FloorPlanning, Chip Desisn, Semiconductor Domain
Tessolve - Manager - RTL Design
Analog Layout Engineer
Staff Engineer - Physical Design
Chennai
Senior SoC Design Engineer - RTL/GDS
Sykatiya Technologies - Physical Design Engineer - Static Timing Analysis
Lead DFT Engineer - SoC/VLSI
STA Engineer - ASIC/SoC Design
Principal/Senior Principal/Design Architect - Analog Circuit Design
Pune/Noida/Hyderabad
ASIC STA Engineer
Mirafra Technologies - Senior/Lead DFT Engineer - VLSI/MBIST
Mirafra Technologies - Physical Design Engineer
Lead DFT Engineer - MBIST/SoC
Principal Analog Mixed Signal Engineer
Multiple Locations
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