ASIC Engineering Digital Designer/ Leader (digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation) :

As a senior level individual contributor, you will work with a diverse team of engineers spanning digital design, analog/mixed-signal design, verification, DFT, physical design, firmware, FPGA, CAD, packaging, and post-silicon validation.

At the concept stage, you will help define the digital architecture, interface requirements, implementation strategy, and design methodology.

During execution, you will own block level and top-level design and block level verification, and support full-chip integration of high-speed IPs such as ODSP, D2D IP, SerDes XSR, SerDes PAM4 integrated drivers/TIA, and control functions.

You will work closely with verification teams to ensure complete functional closure, with physical design teams to support implementation readiness, and with post-silicon teams to help drive successful product bring-up and release to production.

Preferred candidate profile :

- Bachelors or masters degree in electrical engineering, Electronics Engineering, or a related field. Masters degree strongly preferred.

- 8+ years of industry experience with hands-on experience in digital design including FSM and CPU sub-systems, complex SOCs and FPGA validation.

- Familiarity with protocols such as SPI, I2C, APB, AXI, or similar interfaces and high-speed SerDes, Ethernet, D2D PHY IP, and protocols.

- Strong knowledge of ASIC/SoC design flow, including RTL development using SystemVerilog, simulation, lint, CDC/RDC, synthesis, formal/equivalence checking, DFT, and implementation handoff.

- Good understanding of full front-end design and development as well as exposure to full suite of backend tools such as CDC, synthesis, LEC, DFT etc.

- Strong teamwork, communication, and organizational skills.