System Verilog Jobs

System VerilogASICRTLRTL DesignSoCVerilog+4+1

Proxelera - Senior/Principal ASIC/RTL Design Engineer

8 - 13 yrs

Bangalore

System VerilogVerificationUVMSoC VerificationDesign Verification+3

Proxelera - Senior/Principal ASIC Design Verification Engineer - SoC/Subsystem

8 - 13 yrs

Bangalore

System VerilogVerilogSoCVerificationPythonLinuxVLSIRTL+6+3

Emulation Engineer - SoC Verification

5 - 7 yrs

Bangalore

Gate Level Simulation Design Verification Engineer

System VerilogUVMPCI-eASICVerificationPythonGLS+5+2

Multiple Locations

System VerilogDFTUVMASICVerification+3

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DFX/DFT Verification Engineer

7 - 9 yrs

Multiple Locations

Design Verification Engineer - ASIC/SoC

System VerilogUVMVerificationASIC+2

Multiple Locations

PCI-e Design Verification Engineer - Ethernet/CXL/USB/UVM

System VerilogUVMPCI-eASICSoCVerification+4+1

Multiple Locations

Design Verification Engineer - UVM/ASIC

System VerilogUVMASICVerificationPythonRTL+4+1

Multiple Locations

System VerilogASICSoCRTLFirmwareEmbedded CEmbedded C+++5+2

ASIC Engineer

5 - 8 yrs

Bangalore

System VerilogRTLRTL DesignDFTPhysical DesignFirmwareVerilog+5+2

Logic Design Engineer - RTL/DFT

10 - 20 yrs

Bangalore

System VerilogRTL DesignSynopsysASIC+2

Lead RTL Engineer

7 - 15 yrs

Bangalore

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DFT Engineer - Physical Design

5 - 7 yrs

Noida/Pune/Bangalore

System VerilogDFTASICSoCMBISTPhysical DesignVerification+5+2

System VerilogDFXUVMSoCDFTATPGVLSI+5+2

DFX Engineer - UVM/System Verilog

8 - 15 yrs

Bangalore

System VerilogSystemCEmbedded SystemCC+++3

SystemC Engineer - C/C++

2 - 7 yrs

Bangalore

System VerilogAutomation TestingTest ArchitectDesign Verification+2

Technical Lead/Principal DV Engineer - Test Automation Architecture

8 - 10 yrs

Metros

System VerilogSoCASICMicroprocessorVLSI+3

Senior SoC Architect

15 - 18 yrs

Bangalore

System VerilogDFXVerificationDFTSoCASICUVM+5+2

DFX Verification Engineer

4 - 10 yrs

Bangalore

Lead RTL Engineer - System Verilog

System VerilogRTLSynthesisRTL DesignTiming Closure+3

Bangalore

System VerilogASICVerificationATPGPythonUVM+4+1

Senior Verification Engineer - ASIC

8 - 15 yrs

Bangalore