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ASIC Engineer - SoC/Firmware

6 - 10 yrs

Bangalore

RTL DesignASICSystem VerilogSoCFirmware+3

Posted 4 weeks ago

Physical Design Lead - ASIC/VLSI

14 - 24 yrs

Bangalore/Hyderabad

RTL DesignPhysical DesignASICVLSI+2

Posted 4 weeks ago

Western Digital - Staff VLSI Design Engineer

8 - 12 yrs

Bangalore

RTL DesignVLSISoCVerificationUVMSystem VerilogRTLC+6+3

Posted 1 month ago

RTL Design Engineer

3 - 10 yrs

Chennai/Pune

RTL DesignRTLARMSoCFPGAStatic Timing Analysis+4+1

Posted 1 month ago

ASIC RTL Design Lead Engineer

7 - 15 yrs

Noida

RTL DesignASICVerilogSystem Verilog+2

Posted 1 month ago

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Cisco - Digital Designer/Leader - ASIC Engineering

8 - 13 yrs

40-55 LPA

Pune

RTL DesignFPGAASICVerilogFPGA DesignRTLSoCSystem VerilogChipset+7+4

Posted 1 month ago

eInfochips - ASIC RTL Design Engineer

5 - 12 yrs

Multiple Locations

RTL DesignASICVerilogSystem VerilogSoCPhysical Design+4+1

Posted 2 months ago

Happiest Minds Technologies - Senior Engineer - FPGA Design

3 - 5 yrs

Others

RTL DesignFPGAFPGA DesignHDMIEthernet PortStatic Timing Analysis+4+1

Posted 2 months ago

Happiest Minds Technologies - FPGA Design Engineer

5 - 8 yrs

Others

RTL DesignFPGAFPGA DesignRTLVHDL+3

Posted 2 months ago

RTL Design Engineer

5 - 8 yrs

Bangalore

RTL DesignSoCSystem VerilogPhysical Design+2

Posted 2 months ago

Hardware Engineer - RTL/GDS/STA

3 - 6 yrs

Multiple Locations

RTL DesignRTLStatic Timing Analysis+1

Posted 1 month ago

Subject Matter Expert - FPGA/RTL

8 - 13 yrs

Kolkata

RTL DesignFPGARTLVHDLSystem VerilogUVM+4+1

Posted 1 month ago

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ASIC Frontend Design Engineer

5 - 20 yrs

Kolkata

RTL DesignVLSIASICVerilogSoCSystem Verilog+4+1

Posted 1 month ago

Silicon Labs - Lead Engineer - IC Design

8 - 10 yrs

Hyderabad

RTL DesignIC DesignStatic Timing AnalysisPhysical DesignSoC+3

Posted 1 month ago

RTL Design Engineer

3 - 8 yrs

Hyderabad

RTL DesignRTLSystem Verilog+1

Posted 1 month ago

Senior Engineer I - SoC Design

7 - 14 yrs

Bangalore

RTL DesignSoCVLSIEmbedded SystemSystem VerilogVerilogVerification+5+2

Posted 1 month ago

Lead FPGA Design Engineer

5 - 15 yrs

Gurgaon/Gurugram

RTL DesignFPGAFPGA DesignVerilogRTLHardware Design+4+1

Posted 1 month ago

Senior RTL Design Engineer

3 - 6 yrs

Bangalore

RTL DesignVerilogSystem VerilogTiming ClosureSynthesisASIC+4+1

Posted 1 month ago

Proxelera - Senior/Principal ASIC/RTL Design Engineer

8 - 13 yrs

Bangalore

RTL DesignASICRTLSoCVerilogSystem Verilog+4+1

Posted 1 month ago

Logic Design Engineer - RTL/DFT

10 - 20 yrs

Bangalore

RTL DesignRTLDFTPhysical DesignFirmwareVerilogSystem Verilog+5+2

Posted 2 months ago

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