SystemC Modelling Engineer:

Responsibilities:

- Develop and implement SystemC models of hardware architectures and components based on specifications.

- Create and execute simulation test benches to verify the functionality and performance of SystemC models.

- Analyze simulation results, identify potential design issues, and collaborate with hardware architects and designers to propose solutions.

- Contribute to the development of modeling methodologies and best practices within the team.

- Integrate SystemC models with other simulation and verification environments.

- Document modeling efforts, simulation setups, and results clearly and concisely.

- Develop and utilize TLM (Transaction Level Modeling) based simulations for performance analysis and hardware/software co-simulation.

- Collaborate effectively with cross-functional teams, including hardware design, software development, and verification engineers.

Qualifications:

- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

- 5+ years of relevant experience in SystemC modeling and simulation of digital hardware.

- Strong understanding of digital logic design principles and computer architecture concepts (e.g., processor pipelines, memory hierarchies).

- Proven proficiency in SystemC and C/C++.

- Demonstrated experience in developing and debugging SystemC models and simulations for complex systems.

- Familiarity with hardware description languages (HDLs) such as Verilog or VHDL is a plus.

- Solid understanding of simulation and verification methodologies.

- Experience with scripting languages (e.g., Python, Tcl) for automation is desirable.

- Excellent problem-solving and analytical skills.

- Strong communication and interpersonal skills, with the ability to work effectively in a team environment.

- Good understanding in RISC-V architecture, memory systems, interconnect fabrics, Bus subsystems, etc.

Bonus Points:

- Experience with different levels of TLM abstraction (e.g., AT, LT).

- Familiarity with SystemC verification methodologies (SCV).

- Experience with performance analysis and profiling of SystemC models.

- Exposure to FPGA prototyping platforms.

- Experience with hardware/software co-simulation.