ABOUT THE OPPORTUNITY:

We are looking for an experienced semiconductor engineering professional to drive RTL-to-Gate Synthesis, Static Timing Analysis (STA) and Timing Closure for next-generation AI and high-performance computing silicon.

The position will involve working on complex ASIC/SoC architectures, including compute, CPU, VPU, AI accelerators and low-power cores, with a strong focus on implementation quality, timing convergence, power optimisation and sign-off readiness.

MAJOR KEY RESPONSIBILITIES:

- Own and drive end-to-end RTL-to-Gate Synthesis for complex ASIC/SoC, CPU, VPU and AI accelerator designs.

- Lead Static Timing Analysis (STA), timing debug and timing closure across multiple operating modes, process corners, voltage domains and clock domains.

- Drive synthesis setup, constraint development, optimisation, quality checks and gate-level netlist delivery.

- Develop, validate and maintain timing constraints, including SDC (Synopsys Design Constraints) generated clocks, false paths, multicycle paths and interface constraints.

- Optimize designs for Performance, Power and Area (PPA) while meeting aggressive implementation targets.

- Drive Multi-Mode Multi-Corner (MMMC) analysis, timing convergence and sign-off readiness.

- Execute timing ECOs, setup/hold fixes, functional changes and late-stage design closure.

- Implement low-power methodologies, including clock gating, multi-voltage domains, UPF/CPF-based power intent and power-aware synthesis.

- Collaborate with RTL, DFT, Physical Design, Verification, CAD and Architecture teams to resolve implementation and timing challenges.

- Support physical-aware synthesis, placement-aware optimisation and timing correlation with physical design.

- Develop automation scripts using Tcl, Python or Perl to improve synthesis, STA, reporting and debugging workflows.

- Drive improvements in synthesis methodology, timing closure strategies, EDA tools and implementation quality.

MAIN REQUIRED TECHNICAL SKILLS:

- Strong expertise in RTL-to-Gate Synthesis and Static Timing Analysis (STA).

- Hands-on experience in ASIC/SoC implementation and timing closure.

- Expertise in Synopsys and/or Cadence synthesis and STA tool ecosystems.

- Strong understanding of MMMC analysis, SDC constraints, timing debug and sign-off methodologies.

- Experience with setup/hold analysis, timing ECOs, false paths, multicycle paths and generated clocks.

- Understanding of PPA optimisation, low-power synthesis and UPF/CPF-based implementation.

- Experience with hierarchical timing closure, block-level and full-chip timing convergence.

- Strong scripting skills in Tcl, Python and/or Perl.

- Exposure to DFT timing, scan modes and physical design implementation.

PREFERRED CANDIDATE PROFILE:

- Experience working on complex digital ASIC/SoC, CPU, GPU, VPU, AI accelerator or HPC designs.

- Exposure to advanced semiconductor process technologies such as 2nm, 3nm, 5nm or other leading-edge nodes.

- Experience with FinFET technologies, chiplet-based architectures and advanced packaging.

- Understanding of clock tree synthesis, placement, routing and signal integrity.

- Experience with OCV/AOCV/POCV, crosstalk, noise analysis and advanced timing variation methodologies.

- Proven experience driving technical initiatives, mentoring engineers and improving implementation methodologies.

Educational Qualifications:

Bachelor's or Master's degree in Electrical, Electronics, Computer Engineering, VLSI, Computer Science or a related discipline.

Contact:

Nimish Khare, 91-9971997967