Posted on: 17/09/2026
General Summary:
- Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization.
- Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions.
- Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts.
- Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes.
- Good understanding of clocking architecture.
- Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc.
- Well versed with Tcl/Perl Scripting.
- Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers.
- Strong problem-solving skills and good communication skills.
Minimum Qualifications :
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
- OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
- OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
- The individual should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C.
- This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product.
Additional Qualifications :
- Bachelor's/Master's degree in Electrical/Electronic Engineering from reputed institution.
- 12+ years of experience in Physical Design/Implementation.
Total Experience : 9-18 years
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Posted in
Semiconductor/VLSI/EDA
Functional Area
Embedded / Kernel Development
Job Code
1672210