We are looking for an experienced SoC Verification Engineer with strong expertise in SystemVerilog, UVM/OVM, and Object-Oriented Programming (OOP) to work on complex SoC verification projects.

Key Responsibilities:

- Develop and execute comprehensive SoC verification plans and testbenches.

- Perform constrained-random and coverage-driven verification.

- Develop and maintain verification environments using SystemVerilog and UVM/OVM.

- Analyze complex digital designs and identify potential functional issues.

- Debug simulation failures and resolve verification issues effectively.

- Work closely with Design, Architecture, and Verification teams to achieve comprehensive coverage.

- Contribute to verification activities across complex protocols and SoC flows.

Required Skills:

- Strong hands-on experience in SoC Verification.

- Excellent knowledge of SystemVerilog.

- Strong experience with UVM/OVM.

- Good understanding of OOP concepts.

- Experience with complex protocol verification and SoC verification flows.

- Strong understanding of constrained-random testing and functional/coverage-driven verification.

- Experience with simulation tools and debugging methodologies.

Eligibility:

- Minimum 6 years of relevant SoC Verification experience.

- Minimum 5 years of hands-on SoC Verification experience.

- 15 years of full-time education is mandatory.

- Candidates should be willing to work from the Bengaluru office.