Job Summary :

We are looking for a skilled SoC Verification Engineer with 3+ years of experience in ASIC/SoC verification. The ideal candidate should have strong expertise in verification methodologies, SystemVerilog/UVM, and SoC-level verification concepts.

Key Responsibilities :

- Develop and execute verification plans for complex SoC/ASIC designs.

- Create and maintain UVM/SystemVerilog-based verification environments.

- Perform functional, block-level, and SoC-level verification.

- Develop test cases, assertions, and coverage models.

- Debug RTL and verification issues to ensure design quality.

- Work closely with RTL design, architecture, and validation teams.

- Analyze simulation results and ensure coverage closure.

- Participate in design reviews and verification strategy discussions.

- Ensure timely delivery of high-quality verification solutions.

Required Skills :

- 3+ years of experience in SoC/ASIC Verification.

- Strong knowledge of :

1. SystemVerilog

2. UVM methodology

3. Verification concepts

- Experience in :

1. Testbench development

2. Functional verification

3. Coverage-driven verification

- Good understanding of SoC architecture and protocols.

- Experience with debugging and simulation tools.

- Strong analytical and problem-solving skills.