Job Description :

We are looking for an experienced SOC Physical Design Manager to deliver the next generation of cutting-edge graphics designs.

Key Responsibilities :

- Manage the team responsible for Synthesis, Physical Design, timing and Physical closure.

- Manage a large team of internal and external resources.

- Responsible for ensuring the completion of the SOC chip on schedule with high QOR.

- Physical implementation of block level and subsystem level.

- Contribute to Synthesis, Power Reduction, Timing Convergence Floorplan efforts of block and subsystem.

Preferred Experience :

- Proven track record on successfully managing PD teams for complex SOC.

- In-depth understanding and experience for all Physical Design activities for a large, leading technology SOC ASIC chip.

- Strong management, technical problem solving, communication and presentation skills.

- Great team player able to effectively interact and collaborate with partner teams.

- Experienced with Front-End design, DFX and Physical Design Flows.

- Excellent oral, written and presentation skills.

- Extensive experience in handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk.

- Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC LVS), Crosstalk Analysis, EM/IR.

- Hands-on experience on 7nm and sub-7nm projects.

- Experienced in Full Chip Floorplaning, PNR Partitioning / Bump Placement is preferred.

- Experience in Low power and high performance design.

- Responsible for on-time delivery of block-level layouts with exceptional quality.

- Strong self-driving ability and problem-solving skills with high drive for improvements.

Academic Credentials :

- BE/B.Tech/ME/M.TECH or equivalent ECE/EEE.

- 12+ years of experience in Physical Design with at least 2+ years of experience in people management.