In this role, you will be responsible for developing high-performance virtual platforms and architectural models that enable early software development and hardware-software co-design.

You will collaborate closely with cross-functional teams, including RTL designers, verification engineers, and software architects, to ensure that our system-level models accurately reflect silicon behavior.

Your work will directly accelerate our product time-to-market by allowing firmware and OS teams to begin development well before physical silicon is available, playing a critical role in the successful delivery of our next-generation semiconductor solutions.

Key Responsibilities :

- Architect and implement cycle-accurate and transaction-level models using SystemC to facilitate early performance analysis and software validation.

- Develop and maintain TLM 2.0 compliant models to ensure seamless integration and interoperability within our virtual platform ecosystem.

- Collaborate with hardware architects to refine micro-architectural specifications, ensuring that models effectively capture performance bottlenecks and power constraints.

- Optimize simulation speed and model accuracy to provide a robust environment for software teams, thereby reducing the overall development cycle.

- Debug complex system-level issues by analyzing trace data and model behavior, providing actionable insights to the design team to improve silicon quality.

Required Skillset :

- Demonstrate deep expertise in SystemC and TLM 2.0 standards for building sophisticated virtual platforms and architectural simulators.

- Possess a strong understanding of computer architecture, including CPU pipelines, memory hierarchies, and interconnect protocols.

- Exhibit the ability to communicate complex technical concepts clearly to cross-functional stakeholders, fostering a collaborative environment across global teams.

- Hold a Bachelors or Masters degree in Electronics, Electrical Engineering, or Computer Science from a premier institute.

- Show a high degree of adaptability in a hybrid work environment, maintaining productivity and technical excellence while working with distributed engineering teams.

- Bring between 1 - 8 years of hands-on experience in modeling and simulation within the semiconductor industry.