Senior Physical Design Engineer/Lead

Job Title : Senior Physical Design Engineer / Lead

Experience : 9-14 Years

Location : Bangalore / Kochi / Chennai / Pune

Employment Type : Full-time

About the Role :

Neurealm is seeking an experienced Senior Physical Design Engineer / Lead to drive physical implementation activities for complex ASIC/SoC designs.

The role requires strong handson expertise across the complete physical design flow, including floor planning, placement, CTS, routing, timing closure, and physical verification.

The candidate should be capable of independently owning blocks or subsystems, resolving complex implementation challenges, and mentoring junior engineers.

Key Responsibilities :

- Own physical implementation activities for complex blocklevel and toplevel ASIC/SoC designs.

- Drive floor planning, placement, CTS, power planning/routing, and place & route.

- Execute timing analysis and drive timing closure across critical paths.

- Perform Static Timing Analysis (STA) and implement appropriate timing fixes.

- Analyze and resolve setup, hold, congestion, transition, and other implementationrelated issues.

- Drive DRC/LVS closure and collaborate with physical verification teams.

- Optimize designs for performance, power, and area (PPA).

- Work with Innovus, Tempus, and other industrystandard physical design tools.

- Support physical implementation on advanced technology nodes, including 14nm and below.

- Analyze design constraints and identify potential physical implementation risks.

- Collaborate closely with RTL, synthesis, STA, verification, and physical verification teams.

- Participate in design reviews, technical discussions, and implementation planning.

- Mentor junior physical design engineers and provide technical guidance.

- Contribute to methodology improvements and automation initiatives.

- Independently troubleshoot complex physical design issues and drive them to closure.

- Work on designs without a customerspecific flow when required.

Required Skills :

- 9-14 years of experience in Physical Design / ASIC Implementation.

- Strong handson expertise in :

i. Floor planning

ii. Placement

iii. Clock Tree Synthesis (CTS)

iv. Power planning/routing

v. Place & Route

vi. Timing closure

vii. DRC/LVS

- Strong expertise in Static Timing Analysis.

- Handson experience with Cadence Innovus and Tempus.

- Experience working on 14nm or advanced technology nodes.

- Strong understanding of physical verification and signoff methodologies.

- Ability to debug complex implementation and timing issues.

- Experience owning physical design blocks/subsystems independently.

- Strong problemsolving, communication, and collaboration skills.

- Ability to mentor and support junior engineers.

Preferred Skills :

- Experience with advancednode ASIC/SoC implementation.

- Previous experience working on designs without a customerspecific flow.

- Strong understanding of PPA optimization and physical design closure.

- Experience with methodology development and flow improvement.

- Exposure to automation/scripting for physical design activities