Posted on: 24/06/2026
Job Title: Senior Physical Design Engineer (HW Physical Design)
Experience: 5+ Years
Location: Bangalore / Chennai
Employment Type: Full-Time
The candidate should be capable of independently handling blocks/subsystems and collaborating with front-end, DFT, STA, and verification teams to drive successful project execution.
Key Responsibilities:
1. Physical Design Implementation:
- Own and drive complete Physical Design implementation for ASIC/SoC blocks and hierarchical modules.
- Execute end-to-end PNR flow including: 1. Floorplanning 2. Power Planning 3. Placement 4. Clock Tree Synthesis (CTS) 5. Routing 6. Physical Optimization 7. Timing Closure 8. ECO Implementation.
- Analyze and optimize designs for Power, Performance, and Area (PPA).
2. Timing Closure & STA:
- Perform timing analysis and closure for setup, hold, recovery, removal, and clock-related violations.
- Work closely with STA teams to achieve signoff timing requirements.
- Debug and resolve timing bottlenecks across multiple corners and modes.
- Understand and implement timing constraints effectively.
3. Physical Verification & Signoff:
- Perform and support signoff activities including: 1. Static Timing Analysis (STA) 2. Physical Verification (DRC/LVS) 3. Power Analysis 4. Formal Verification (LEC) 5. Low Power Verification 6. Signal Integrity Analysis 7. EM/IR Analysis.
- Ensure design compliance with foundry signoff requirements and tape-out readiness.
4. Power & Low Power Design:
- Develop and verify power distribution networks (PDN).
- Analyze power integrity and optimize for leakage and dynamic power.
- Support low-power methodologies such as: 1. UPF/CPF implementation 2. Power gating 3. Multi-voltage designs 4. Retention and isolation strategies.
5. Design Optimization:
- Optimize congestion, timing, area, and power during implementation stages.
- Perform root-cause analysis and develop solutions for implementation challenges.
- Support ECO generation and implementation for late-stage design changes.
6. Automation & Scripting:
- Develop and maintain automation scripts using TCL, Perl, Shell, or Python.
- Create utilities to improve Physical Design productivity and flow efficiency.
- Automate repetitive tasks and reporting mechanisms.
7. Cross-Functional Collaboration:
- Collaborate with RTL, DFT, STA, Verification, and CAD teams.
- Participate in design reviews and implementation planning.
- Work closely with global teams to resolve design and implementation issues.
Required Technical Skills:
1. Physical Design Expertise:
- Strong hands-on experience in: 1. Floorplanning 2. Power Planning 3. Placement 4. CTS 5. Routing 6. Timing Closure 7. ECO Flows.
- Experience in handling block-level and hierarchical physical design implementation.
2. Signoff Knowledge:
- Strong understanding of: 1. STA 2. Power Analysis 3. Formal Verification (LEC) 4. Physical Verification (DRC/LVS) 5. Low Power Verification 6. EM/IR Analysis 7. Signal Integrity Analysis.
3. EDA Tools:
- Experience with one or more industry-standard tools: 1. Physical Design 2. Cadence Innovus 3. Synopsys ICC2.
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Posted in
Semiconductor/VLSI/EDA
Functional Area
Embedded / Kernel Development
Job Code
1648066