Senior DFT Engineer/Lead - ASIC/SoC

Job Title : Senior DFT Engineer / Lead

Experience : 9-14 Years

Location : Bangalore / Kochi / Chennai / Pune

Employment Type : Full-time

About the Role :

We are seeking an experienced Senior DFT Engineer / Lead to drive DFT implementation, ATPG, coverage closure, MBIST, and test architecture activities for complex ASIC/SoC designs.

The candidate should be capable of independently owning DFT blocks and flows while collaborating with design, verification, synthesis, and ATE teams.

Key Responsibilities :

- Own DFT implementation activities across complex ASIC/SoC designs.

- Drive scan architecture, scan insertion, ATPG generation, and coverage closure.

- Generate and analyze ATPG patterns for Stuck-At and At-Speed fault models.

- Analyze test coverage and implement strategies to improve coverage and test quality.

- Lead MBIST insertion, configuration, simulation, and debug.

- Implement and validate Boundary Scan, TAP Controller, and IEEE 1500/P1500 structures.

- Drive both RTL-based and netlist-based DFT insertion flows.

- Perform DFT simulations with and without SDF and debug complex simulation failures.

- Work with synthesis and formal verification teams to ensure DFT implementation correctness.

- Support DC characterization and associated test requirements.

- Generate TDL patterns/data for ATE and work closely with ATE teams during bring-up.

- Support silicon bring-up and debug test-related issues.

- Work with DFT tools from Mentor/Siemens EDA, Synopsys, and Cadence.

- Develop automation scripts using Perl and TCL to improve DFT productivity.

- Perform and review Static Timing Analysis for DFT-related paths where required.

- Collaborate with RTL, physical design, STA, verification, ATE, and product engineering teams.

- Mentor junior DFT engineers and contribute to DFT methodology and flow improvements.

Required Skills :

- 9-14 years of strong experience in DFT / ASIC / SoC Test.

- Extensive hands-on experience with Scan insertion and ATPG.

- Strong expertise in Stuck-At and At-Speed fault models and coverage analysis.

- Strong experience with MBIST insertion and simulation.

- Experience with Boundary Scan, TAP Controller, and IEEE 1500/P1500.

- Strong knowledge of RTL and netlist-based DFT insertion flows.

- Experience with DFT simulation with and without SDF.

- Good understanding of synthesis and formal verification tools.

- Experience with ATE/TDL generation and silicon bring-up.

- Strong scripting skills in Perl and TCL.

- Hands-on experience with DFT tools from Mentor/Siemens EDA, Synopsys, and Cadence.

- Good understanding of Static Timing Analysis.

- Strong debugging, problem-solving, and communication skills.

Preferred Skills :

- Experience owning DFT implementation for complete blocks/subsystems.

- Exposure to advanced-node SoC/ASIC designs.

- Experience working directly with ATE and product engineering teams.

- Experience developing or improving DFT flows and automation.

- Mentoring and technical leadership experience