Job Description :

As a Verification engineer, you should have the hands-on experience related to block level, sub-system level and chip top level verification.

- Development and working with object-oriented verification languages (System Verilog, UVM).

- Mandatory background in Mixed Signal devices.

- Good at debugging design and environment related issues.

- Should be good at Digital basics.

- Develop environment and tests for block level verification and extend the same to block and chip top level verification.

- Good understanding of RAL, Code coverage and functional coverage and implementing the same.

- Scripting using Perl, Python and Shell.

- Simulations using gate level netlist at various PVT corners.

- Generation of vcd files for power analysis.

- Good understanding of DFT concepts and running ATPG simulations.

- Working with analog and architecture teams to handle integration of netlist and models into test environment.

- Usage of FPGA based validation platform in the lab.

- Handling of bring-up and characterization lab activities.

Eligible candidates kindly send your resumes to preetha@nobleedgetalent.com