Job Summary :

We are seeking an experienced RTL Design Engineer with expertise in RISC-V CPU Architecture to contribute to the design and development of next-generation processor cores. The ideal candidate will have strong experience in CPU micro-architecture, RTL development, performance optimization, and SoC integration, along with the ability to lead architectural decisions and mentor engineering teams.

Key Responsibilities :

Micro-Architecture Design & Specification :

- Define and develop detailed micro-architecture specifications for RISC-V CPU components.

- Design advanced CPU features including :

1. Branch Prediction Units

2. Instruction Scheduling Mechanisms

3. Register Renaming Logic

4. Vector Execution Units

- Collaborate with architecture teams to translate high-level architectural concepts into RTL specifications.

- Evaluate performance, power, and area (PPA) trade-offs during architecture development.

RTL Development & Implementation :

- Develop and implement RTL using Verilog/SystemVerilog.

- Design optimized CPU pipelines, execution units, and datapath logic.

- Ensure RTL meets timing, power, and performance objectives.

- Build modular, scalable, and maintainable RTL architectures.

CPU Architecture Evaluation :

- Analyze and benchmark various RISC-V CPU implementations, including :

1. In-order Architectures

2. Out-of-order Architectures

3. Superscalar Architectures

- Perform architecture performance evaluation using simulation and modeling tools.

- Collaborate with performance teams to validate design decisions against real-world workloads.

Virtualization & Security :

- Develop hardware-assisted virtualization features.

- Integrate security extensions supporting secure execution environments.

- Implement hardware-level security mechanisms and ensure compliance with architectural security requirements.

SoC Integration :

- Design and integrate CPU infrastructure components including :

1. AXI

2. CHI

3. Clock Architecture

4. Reset Architecture

5. Power Management

- Collaborate with SoC integration teams to ensure seamless interoperability.

- Optimize clocking, reset, and power architectures for efficient system operation.

Design Lifecycle :

- Participate throughout the complete CPU design lifecycle, including :

1. Architectural Exploration

2. RTL Design

3. Functional Verification

4. Performance Validation

5. Physical Design Readiness

- Support verification environments, simulation frameworks, and debugging activities.

- Work closely with verification teams to improve coverage and design quality.

Technical Leadership :

- Mentor junior engineers on CPU architecture and RTL design best practices.

- Establish coding standards and design methodologies.

- Drive technical decision-making for complex architectural challenges.

- Maintain comprehensive design documentation.

Required Skills :

1. CPU Architecture :

- RISC-V Architecture, CPU Micro-Architecture, In-order & Out-of-order Processors, Superscalar Architectures, Branch Prediction, Register Renaming, Instruction Scheduling, Vector Processing.

2. RTL Design :

- Verilog, SystemVerilog, RTL Design, CPU Pipelines, Datapath Design.

3. SoC Design :

- AXI, CHI, Clock Architecture, Reset Architecture, Power Management, SoC Integration.

4. Verification & Performance :

- Functional Verification, Performance Modeling, CPU Benchmarking, Simulation & Debugging.

5. Leadership :

- Technical Leadership, Design Reviews, Mentoring, Documentation.

Preferred Skills :

- Knowledge of Physical Design flow.

- Experience with virtualization and security extensions.

- Familiarity with advanced processor optimization techniques.