Analog Circuit Design (Principal / Sr. Principal / Design Architect / Design Manager / Senior Design Manager)

Experience : 10 - 17 Years

Location : Hyderabad / Noida / Pune (Hyderabad Preferred)

Education : BE / B.Tech / ME / M.Tech / MS / PhD in Electrical, Electronics, Microelectronics, VLSI, or related disciplines

About the Role :

We are seeking experienced Analog/Mixed-Signal Design Engineers and Technical Leaders to drive the development of next-generation high-speed interface IPs across advanced technology nodes. The role involves architecture, design, implementation, debug, and delivery of industry-leading connectivity and memory interface solutions spanning UCIe, Die-to-Die (D2D), PCIe, DDR/LPDDR, HBM and SerDes-based interfaces.

Depending on experience and leadership capabilities, candidates may be considered for Principal Engineer, Senior Principal Engineer, Design Architect, Design Manager, or Senior Design Manager positions.

Technical Requirements :

High-Speed Interface Expertise :

In-depth understanding of high-speed analog and mixed-signal circuits used in :

- UCIe (Universal Chiplet Interconnect Express)

- Die-to-Die (D2D) interfaces

- PCIe Gen3/4/5/6/7

- DDR4/DDR5/LPDDR4/LPDDR5/LPDDR6

- HBM memory interfaces

- Advanced SerDes architectures

Circuit Design Expertise :

Hands-on experience designing and optimizing :

- High-speed I/O circuits

- TX/RX datapaths

- Sampling circuits and comparators

- Equalizers (CTLE, DFE, FFE)

- Clocking architectures

- PLLs, DLLs, CDRs

- Voltage regulators and reference circuits

- Low-power high-speed analog circuits

- Clock distribution and timing circuits

System & Interface Knowledge :

Strong understanding of :

- Signal Integrity (SI)

- Power Integrity (PI)

- Jitter analysis and timing closure

- Package and channel effects

- ESD and Reliability

- AMS verification methodologies

- Silicon characterization and debug

- Performance, Power, Area (PPA) optimization

Process & Technology Experience :

Experience working on advanced technology nodes such as :

- 16nm

- 12nm

- 10nm

- 7nm

- 5nm

- 4nm

- 3nm

- Advanced FinFET and GAA technologies

Knowledge of :

- Technology migration and IP porting

- Design reuse methodologies

- Analog automation and AI-assisted design methodologies

- Functional mapping and technology scaling methodologies

Leadership Expectations (Principal / Sr Principal) :

- Technical ownership of complex IPs and subsystems.

- Drive architecture reviews, design reviews, and design closure.

- Lead cross-functional execution involving :

1. Analog Design

2. Layout

3. AMS Verification

4. Digital Design

5. Physical Design

6. Product Engineering

- Define technical strategy and execution plans.

- Mentor and grow junior and mid-level engineers.

- Drive innovation, patents, publications, and methodology improvements.