Principal/Lead RTL Design Engineer - ASIC/SoC

Role : Principal / Lead RTL Design Engineer

About the Role :

We are looking for a highly experienced Principal / Lead RTL Design Engineer to provide technical leadership for complex ARM-based ASIC/SoC development programs. The role involves driving RTL architecture and implementation, owning critical subsystems, defining design methodologies, and providing technical direction across the complete design lifecycle.

Key Responsibilities :

- Provide technical leadership for RTL architecture, design, and implementation of complex ASIC/SoC projects.

- Own and drive design of critical IP blocks, subsystems, and SoC components from architecture through implementation.

- Translate high-level system and micro-architectural specifications into optimized and scalable RTL.

- Lead integration of ARM core-based designs into complex SoC architectures.

- Define and drive implementation of AMBA AXI, AHB, and APB interfaces and interconnects.

- Review and optimize RTL for performance, power, area, scalability, and design quality.

- Establish and enforce RTL coding standards, design methodologies, and review processes.

- Lead Lint and CDC closure across critical designs and subsystems.

- Drive ASIC synthesis, Static Timing Analysis, timing closure, and design optimization.

- Analyze and resolve complex timing and implementation challenges in collaboration with physical design teams.

- Drive formal/equivalency checking and ensure design consistency across implementation stages.

- Provide technical direction for FPGA prototyping and FPGA-based development where required.

- Lead complex RTL debugging and root-cause analysis across design and integration environments.

- Collaborate with architecture, verification, physical design, firmware, and system engineering teams.

- Conduct design and code reviews and provide technical guidance to senior engineers.

- Mentor engineers and establish best practices for RTL development and SoC integration.

- Identify technical risks, dependencies, and design bottlenecks and drive their resolution.

- Contribute to project planning, technical estimation, resource planning, and milestone execution.

- Drive continuous improvement of RTL design methodologies, automation, and design quality.

Required Skills :

- 15 - 18 years of experience in RTL Design / ASIC / SoC Design.

- Expert-level proficiency in Verilog/VHDL and RTL design methodologies.

- Deep expertise in ARM-based SoC architecture and integration.

- Extensive experience with AMBA AXI, AHB, and APB protocols.

- Strong expertise in Lint, CDC, ASIC synthesis, and Static Timing Analysis.

- Extensive experience with formal/equivalency checking.

- Strong experience in FPGA design and/or FPGA prototyping.

- Deep understanding of digital architecture, microarchitecture, SoC integration, and design closure.

- Strong expertise in debugging complex RTL and system-level design issues.

- Proven ability to technically lead complex design projects and mentor senior engineers.

- Strong cross-functional communication and stakeholder management skills.

Preferred Skills :

- Experience architecting and implementing complex ARM-based SoCs.

- Experience with high-performance, high-speed, or power-sensitive designs.

- Strong understanding of PPA optimization and timing closure.

- Experience leading design methodology and process improvements.

- Experience working with geographically distributed engineering teams.

- Strong technical leadership and problem-solving capabilities.