Physical Design Lead

We are looking for an experienced Physical Design Lead with a minimum of 14+ years of expertise in ASIC/VLSI physical design and a strong full-chip implementation background. The role will be responsible for driving physical implementation, timing closure, power convergence, and sign-off of complex, high-frequency and low-power SoCs.

Key Responsibilities :

- Lead full-chip physical design and implementation of complex ASIC/SoC designs from RTL to GDSII.

- Drive timing closure through physical synthesis, Place & Route, timing optimization and ECO implementation.

- Own and drive the complete front-end to back-end implementation flow, including RTL synthesis, formal verification, floorplanning, netlisting, placement and routing, timing constraints, timing analysis, power convergence, and sign-off.

- Lead physical design closure for large and complex designs operating at 1 GHz+ frequencies.

- Own Clock Tree Synthesis (CTS) and clock distribution for high-frequency designs.

- Work closely with Systems and Application teams to develop timing-closure-friendly SoC architectures and IO interfaces.

- Drive IO planning and IO pin optimization in alignment with overall chip architecture and timing requirements.

- Define and streamline timing sign-off criteria, timing analysis methodologies and implementation flows.

- Develop and enhance automation scripts for timing closure and automatic ECO generation.

- Collaborate with ASIC vendors and internal design teams to resolve implementation challenges and achieve schedule, PPA and sign-off targets.

Required Skills & Experience :

- 14+ years of relevant experience in ASIC/VLSI Physical Design.

- Proven full-chip physical design experience is mandatory.

- Strong hands-on experience with the RTL-to-GDSII physical implementation flow.

- Expertise in physical synthesis, floorplanning, placement & routing, CTS, timing analysis, ECO implementation, and power optimization.

- Experience with 1 GHz+ high-frequency designs is highly desirable.

- Experience with CPU, GPU and/or complex ASIC/SoC designs in high-performance and low-power environments.

- Strong scripting/automation skills using Tcl, Python, Perl or similar languages.

- Strong understanding of PPA optimization and design trade-offs.

Preferred Technical Expertise :

- Experience with industry-standard Physical Design / Place & Route tools.

- Strong understanding of advanced-node physical design challenges.

- Experience handling complex timing scenarios and multi-corner/multi-mode timing closure.