Job Description :

We are looking for a highly skilled Physical Design Engineer with strong hands-on experience in end-to-end ASIC Physical Design implementation for advanced technology nodes. The ideal candidate should have expertise in block-level/sub-chip level implementation, timing closure, physical verification, ECO execution, and signoff activities.

Key Responsibilities :

- Perform complete Physical Design flow from Netlist to GDSII for block/sub-chip level designs.

- Handle Floorplanning, Power Planning, Placement, CTS (Clock Tree Synthesis), Routing, and Physical Verification activities.

- Drive timing closure across all design stages and achieve PPA (Power, Performance, Area) targets.

- Perform Static Timing Analysis (STA) and resolve setup/hold violations.

- Execute ECO implementation and timing convergence activities.

- Perform Physical Verification and achieve DRC/LVS clean signoff.

- Analyze and resolve congestion, timing, SI, IR drop, and power-related issues.

- Collaborate with RTL, Synthesis, DFT, STA, and Signoff teams to achieve project milestones.

- Debug implementation issues and drive closure independently.

- Own and deliver block-level physical design activities with minimal supervision.

- Support tapeout activities and foundry signoff requirements.

Mandatory Skills :

- Strong hands-on experience in Physical Design (P&R) at block/sub-chip level.

- Expertise in Static Timing Analysis (STA) and timing closure.

- Experience in Physical Verification (DRC/LVS closure).

Strong knowledge of :

1. Floorplanning

2. Power Planning

3. Placement Optimization

4. Clock Tree Synthesis (CTS)

5. Routing

6. Signal Integrity

7. ECO Implementation

8. Signoff Methodologies

Hands-on experience with :

1. Cadence Innovus

2. Synopsys PrimeTime

- Ability to independently own and close Physical Design blocks.

- Strong debugging and problem-solving skills.

Preferred Skills :

- Experience with advanced technology nodes (28nm/16nm/7nm/5nm).

- Knowledge of MCMM timing analysis.

- Experience with IR Drop, EM, Crosstalk, Noise Analysis.

- Exposure to Synopsys ICC2/Fusion Compiler is a plus.

- Scripting knowledge in Tcl, Perl, Python, or Shell.

- Experience with low-power designs and UPF/CPF methodologies.

- Previous tapeout experience is highly preferred.