Physical Design Engineer - RTL/DFT
Posted on: 19/05/2026
Job Description
Description :
We are hiring #PhysicalDesign (#PD) leads / Managers
These positions supports #Semiconductor design teams working with advanced process nodes and industry-standard #EDA tools to deliver timing, power, and signal-integrity optimized #tapeouts.
Job Overview :
A Physical Design Lead / Manager role responsible for leading block and chip-level physical implementation from #RTL to #GDSII, ensuring methodology compliance and design signoff across #STA, #LVS, #DRC, and power verification.
What you'll do :
- Lead block and chip-level physical design flows from RTL through GDSII signoff
- Apply and enforce #AMD-compatible methodology and quality standards across designs
- Drive floorplanning, placement, #CTS, routing, and timing optimization activities
- Address #IR drop, #EM closure, congestion, and signal-integrity challenges
- Coordinate STA, LVS, DRC, and power verification signoff with EDA tools
- Collaborate with front-end, #DFT, and verification teams for integrated delivery
- Track design schedules, quality metrics, and technical risk mitigation
- Mentor and provide technical guidance and reviews to PD team members
Who you are :
- Proficient in #Innovus, #ICC2, #PrimeTime, #Voltus, #RedHawk, and #Calibre tools
- Strong understanding of timing analysis, power optimization, and congestion management
- Experienced with advanced process nodes such as #7nm, #5nm, or below
- Skilled at debugging complex physical-design issues and proposing solutions
- Effective communicator and coordinator across multi-disciplinary engineering teams
- Comfortable driving technical decisions and supporting team execution
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Posted by
170
Posted in
Semiconductor/VLSI/EDA
Functional Area
Embedded / Kernel Development
Job Code
1637018
