Physical Design Engineer - Floor Planning

Role Overview :

As a Senior Physical Design Engineer, you will lead the end-to-end implementation of complex blocks and full-chip designs, ensuring optimal performance, power, and area (PPA) targets are met.

You will work closely with cross-functional teams, including RTL design, DFT, and timing analysis groups, to drive designs from netlist to GDSII.

Your contributions will directly influence the reliability and efficiency of high-end silicon products, playing a critical role in the successful tape-out of sophisticated designs for our global client base in Bangalore.

Key Responsibilities :

- Drive the complete physical implementation flow, including placement, clock tree synthesis (CTS), and routing, to meet stringent timing and power constraints.

- Perform comprehensive sign-off analysis, including static timing analysis (STA) and physical verification, to ensure zero-defect silicon delivery.

- Mentor junior engineers by providing technical guidance on complex implementation challenges and design methodology improvements.

- Collaborate with internal stakeholders to resolve design bottlenecks and improve the overall efficiency of the physical design cycle.

Required Skillset :

- Proficiency in industry-standard EDA tools, specifically Innovus, for managing complex physical design flows from synthesis to sign-off.

- Strong analytical skills in floor planning and congestion management to ensure robust design convergence.

- Ability to communicate complex technical concepts effectively to cross-functional teams and stakeholders to ensure project alignment.

- Proven track record of working in a fast-paced, collaborative environment, with the flexibility to adapt to evolving project requirements in our Bangalore office.

- Bachelor's or Master's degree in Electronics and Communication Engineering or a related field, with 7 to 12 years of hands-on experience in physical design.