Role Overview :

As a Physical Design Engineer based in Bangalore, you will be at the heart of our silicon development lifecycle, transforming complex RTL designs into high-performance, power-efficient physical layouts. You will collaborate closely with cross-functional teams, including RTL design, verification, and timing closure experts, to navigate the challenges of advanced process nodes. Your daily contributions will directly influence the success of our next-generation semiconductor products, ensuring that our silicon meets stringent performance, power, and area (PPA) targets before reaching our global customers.

Key Responsibilities :

- Execute comprehensive floor planning strategies to optimize chip area and signal integrity for high-speed designs.

- Perform logic synthesis and physical implementation to ensure the design meets all timing and power constraints.

- Drive the physical verification process, including DRC, LVS, and ERC checks, to guarantee manufacturing readiness and yield.

- Collaborate with RTL design teams to resolve implementation bottlenecks and improve design convergence cycles.

- Analyze and mitigate signal integrity issues, such as crosstalk and IR drop, to ensure long-term reliability of the silicon.

Required Skillset :

- Demonstrated expertise in the end-to-end physical design flow, specifically in synthesis, floor planning, and place-and-route.

- Strong proficiency in handling complex timing constraints and resolving setup and hold violations in high-frequency designs.

- Ability to communicate technical challenges effectively across multidisciplinary teams to drive consensus on design trade-offs.

- A Bachelor's or Master's degree in Electronics or Electrical Engineering with a deep understanding of semiconductor physics.

- Proven capability to adapt to a fast-paced, collaborative office environment in Bangalore, maintaining high standards of precision and technical rigor.