Job Title : PCIe Design Verification Engineer Ethernet / CXL / USB | SystemVerilog | UVM

Experience : 7-10 Years (Minimum 3 years of hands-on experience in PCIe, Ethernet, CXL, or USB protocol verification)

Job Location : Bengaluru | Visakhapatnam (Vizag) | Kochi | Ahmedabad

Employment Type : Full-Time

Job Summary :

We are looking for an experienced Design Verification Engineer with expertise in high-speed interface and networking protocol verification, including PCIe, Ethernet, CXL, and USB. The ideal candidate should have strong hands-on experience in SystemVerilog, UVM, and protocol-based verification for complex ASIC/SoC designs. You will be responsible for developing scalable verification environments, validating protocol compliance, and ensuring first-pass silicon success through comprehensive functional verification.

Key Responsibilities :

- Verify PCIe, Ethernet, CXL, and USB IPs/subsystems using SystemVerilog and UVM.

- Develop reusable UVM-based verification environments, testbenches, and verification components.

- Create directed and constrained-random test cases to validate protocol functionality.

- Develop verification plans, assertions, scoreboards, and coverage models.

- Debug RTL, protocol, and simulation failures to identify root causes.

- Execute regressions, analyze functional coverage, and drive verification closure.

- Validate protocol compliance and interoperability across supported interfaces.

- Collaborate with Design, Architecture, Firmware, and Physical Design teams to resolve verification issues.

- Participate in design and verification reviews and contribute to methodology improvements.

Required Skills :

- 7-10 years of experience in ASIC/SoC Design Verification.

- Minimum 3 years of hands-on experience in PCIe, Ethernet, CXL, or USB protocol verification.

Strong expertise in one or more of the following protocols :

1. PCI Express (PCIe)

2. Ethernet

3. Compute Express Link (CXL)

4. USB

- Excellent programming skills in System Verilog (SV).

- Strong hands-on experience with UVM (Universal Verification Methodology).

- Experience in developing reusable UVM verification environments.

- Strong debugging skills for RTL, protocol, and simulation issues.

- Experience with functional coverage, assertions, and constrained-random verification.

- Good understanding of ASIC/SoC verification methodologies.

Preferred Skills :

- Experience leading verification teams or owning verification projects.

- Familiarity with EDA tools such as Synopsys VCS, Cadence Xcelium, Verdi, or equivalent.

- Experience with scripting using Python, Perl, or Shell.

- Knowledge of additional verification methodologies and automation frameworks.

- Strong analytical and debugging skills.

- Excellent communication and interpersonal abilities.

- Ability to work in a fast-paced environment and manage multiple priorities.

Education :

- B.E./B.Tech/M.E./M.Tech in Electrical Engineering, Electronics & Communication, VLSI, Microelectronics, or a related discipline.