Neurealm - Principal/Lead DFT Engineer

Principal / Lead DFT Engineer

Experience : 15 - 18 Years

Location : Bangalore / Kochi / Chennai / Pune

Job Type : Full-time

About the Role :

We are looking for a highly experienced Principal / Lead DFT Engineer to provide technical leadership for DFT architecture, implementation, ATPG, MBIST, test coverage, and silicon bring-up activities across complex ASIC/SoC programs.

The role requires deep hands-on expertise in DFT methodologies combined with the ability to define test strategies, lead implementation, resolve complex issues, and mentor senior engineers.

Key Responsibilities :

- Define and drive the overall DFT architecture, methodology, and implementation strategy for complex ASIC/SoC programs.

- Lead scan architecture, scan insertion, ATPG generation, and test coverage closure.

- Drive ATPG development for Stuck-At, At-Speed, and other applicable fault models.

- Analyze coverage gaps and define strategies to achieve DFT/test coverage targets.

- Lead MBIST architecture, insertion, simulation, and debug.

- Drive implementation of Boundary Scan, TAP Controller, and IEEE 1500/P1500 architectures.

- Own RTL and netlist-based DFT insertion methodologies and sign-off.

- Lead DFT simulation with and without SDF and resolve complex simulation and implementation issues.

- Collaborate with synthesis and formal verification teams to ensure DFT correctness and design equivalence.

- Drive DC characterization and support test-related characterization requirements.

- Lead TDL generation and ATE integration activities.

- Work closely with ATE, product engineering, validation, and silicon bring-up teams to debug test issues.

- Provide technical leadership during silicon bring-up and production test enablement.

- Drive usage and methodology development across Mentor/Siemens EDA, Synopsys, and Cadence DFT tools.

- Develop and enhance DFT automation using Perl and TCL.

- Lead DFT-related Static Timing Analysis and timing closure activities where applicable.

- Define DFT quality metrics, sign-off criteria, and implementation best practices.

- Review DFT architecture, implementation plans, ATPG results, coverage reports, and sign-off data.

- Mentor senior and junior DFT engineers and provide technical direction.

- Collaborate with RTL, physical design, STA, verification, architecture, ATE, and product engineering teams.

- Identify technical risks and drive resolution of complex DFT challenges throughout the project lifecycle.

Required Skills :

- 15 - 18 years of strong experience in DFT / ASIC / SoC Test Engineering.

- Expert-level knowledge of Scan, ATPG, MBIST, Boundary Scan, and IEEE 1500/P1500.

- Extensive experience with Stuck-At and At-Speed ATPG and coverage optimization.

- Deep experience with DFT insertion at RTL and netlist levels.

- Strong expertise in DFT simulation with and without SDF.

- Strong understanding of synthesis and formal verification/equivalence methodologies.

- Extensive experience with ATE/TDL generation and silicon bring-up.

- Strong knowledge of Mentor/Siemens EDA, Synopsys, and Cadence DFT tools.

- Expert scripting skills in Perl and TCL.

- Strong knowledge of Static Timing Analysis and DFT timing requirements.

- Proven ability to lead complex DFT programs and provide technical direction.

- Strong debugging, problem-solving, communication, and stakeholder management skills.

Preferred Skills :

- Experience defining DFT architecture for complex SoCs.

- Experience with advanced technology nodes and high-complexity designs.

- Strong experience in production test and silicon debug.

- Experience establishing DFT methodologies and automation frameworks.

- Proven experience mentoring senior engineers and leading technical teams