Department : DFT Engineer

Reports To : BU Head

Location : Bengaluru

Employment Type : Full Time

Job Summary :

The DFT Engineer will be responsible for Design-for-Test (DFT) architecture, DFT insertion, integration, analysis, and sign-off for the full chip, including PHY and third-party IP DFT boundaries. The role requires strong hands-on experience across scan architecture, scan compression, PHY DFT integration, BIST, MBIST, ATPG, JTAG/boundary scan, and DFT coverage analysis. The candidate will work across the chip-level DFT flow to ensure that the design incorporates the required test structures and achieves the specified DFT coverage requirements.

Key Skills & Responsibilities :

- Scan chain insertion and compression (Tessent) across multi-clock digital logic : Strong hands-on experience with scan chain insertion and scan compression using Siemens Tessent, particularly across multi-clock digital logic. The candidate should understand scan architecture, scan chain implementation, compression logic, and associated DFT structures across complex designs containing multiple clock domains.

- ASA PHY DFT integration : Experience with ASA PHY DFT integration is required. The candidate will understand the DFT requirements of the ASA PHY and integrate the required DFT structures and controls into the overall chip-level DFT architecture, ensuring correct connectivity, control, accessibility, and test operation.

- ASA IP DFT ports : Hands-on experience with ASA IP DFT ports and their integration into the chip-level DFT environment. The candidate should understand DFT interfaces exposed by ASA IPs and ensure that these ports are correctly connected and controlled as part of the overall test architecture.

- BIST PCS-PMA bus isolation : Experience with BIST and PCS-PMA bus isolation. The candidate should understand Built-In Self-Test requirements and isolation of relevant PCS-PMA buses during test modes, ensuring that test modes operate without unintended interaction with functional data paths.

- Memory BIST (MBIST) for internal SRAMs/FIFOs; ATPG pattern generation and fault simulation : Hands-on experience with Memory Built-In Self-Test (MBIST) for internal SRAMs and FIFOs. The role also includes ATPG pattern generation and fault simulation, analyzing fault coverage, identifying test gaps, debugging ATPG issues, and supporting DFT coverage closure.

- IEEE 1149.1 JTAG controller integration; boundary scan for automotive test coverage : Experience integrating an IEEE 1149.1 JTAG controller and implementing boundary scan functionality. The candidate should understand JTAG architecture and the role of boundary scan in chip-level testing, debug, manufacturing test, and external connectivity validation, with emphasis on automotive test coverage.

- Siemens Tessent or Synopsys DFT Compiler; prior automotive-grade DFT (AEC-Q100) experience preferred : Hands-on experience with Siemens Tessent or Synopsys DFT Compiler. The candidate should have practical experience across DFT implementation flows, including insertion, configuration, analysis, debugging, and closure. Prior automotive-grade DFT experience, particularly aligned with AEC-Q100 expectations, is preferred.

- Coverage requirement for DFT modes will be specified by SiliconAuto : The candidate will be responsible for working toward the DFT mode coverage requirements specified by SiliconAuto. This includes understanding coverage targets, analyzing coverage reports, identifying gaps, and implementing appropriate DFT/test solutions to achieve specified requirements.

- Full-chip DFT architecture, integration and sign-off : Contribute to the overall full-chip DFT architecture, integration, and sign-off process, considering DFT requirements across digital logic, PHYs, third-party IPs, memories, scan structures, BIST mechanisms, and test-access infrastructure.

Qualification & Experience :

- B.E / B.Tech / M.E / M.Tech

- 7 - 8 Years

Benefits : As per company policy

Travel Requirements : As per client requirement