Job Overview :

We are looking for experienced DFT Engineers to join our VLSI team. The role involves DFT architecture, implementation, verification, and silicon bring-up/debug across various levels of experience.

Key Responsibilities :

- Develop and implement Design-for-Test (DFT) architecture and methodologies for complex SoCs.

- Work on Scan insertion, ATPG, MBIST, LBIST, JTAG/Boundary Scan, and test compression.

- Perform DFT RTL integration, synthesis, and implementation.

- Develop and debug ATPG patterns, analyze coverage, and resolve test-related issues.

- Work on scan chain analysis, test modes, constraints, and DFT timing.

- Perform DFT verification including simulations, ATPG validation, and coverage analysis.

- Debug DFT-related issues across RTL, gate-level, and physical implementation stages.

- Collaborate with RTL, STA, Physical Design, Verification, and Silicon teams.

- Support DFT signoff, production test requirements, and silicon bring-up/debug.

- Develop scripts and automation using TCL, Python, Perl, or Shell where applicable.

- For senior/lead roles, drive DFT methodology, architecture, technical reviews, and project execution.

Required Skills :

- Strong understanding of DFT concepts and methodologies.

- Hands-on experience with Scan, ATPG, MBIST, LBIST, JTAG, Boundary Scan, and Compression.

- Experience with industry-standard DFT tools such as Synopsys TestMAX/TetraMAX, Cadence Modus, Mentor Tessent, or equivalent.

- Good understanding of STA, synthesis, RTL, and physical design flows.

- Experience with DFT constraints, test clocks, test modes, scan chains, and coverage analysis.

- Good scripting/programming skills in TCL, Python, Perl, or Shell.

- Strong debugging, problem-solving, and communication skills.

Experience Levels :

- 3 - 6 Years : DFT implementation, scan insertion, ATPG, pattern generation, coverage analysis, and debugging.

- 6 - 10 Years : End-to-end DFT implementation, complex SoC DFT, methodology development, and technical ownership.

- 10 - 14 Years : DFT architecture, project ownership, advanced ATPG/MBIST/JTAG, signoff, and cross-functional leadership.

- 14 - 17 Years : DFT technical leadership/architecture, methodology definition, customer interaction, and mentoring of DFT teams.

Education :

- B. Tech/M. Tech in Electronics, Electrical Engineering, VLSI, or a related field.

Preferred :