We are seeking a highly experienced Lead DFT Engineer / DFT Manager to drive end-to-end Design for Testability (DFT) strategy, architecture, implementation, and signoff for complex SoC and IP development programs.

The ideal candidate will possess deep hands-on expertise in DFT methodologies, strong technical leadership capabilities, and experience leading cross-functional teams to deliver high-quality silicon solutions.

Key Responsibilities :

DFT Architecture & Strategy :

- Lead end-to-end DFT architecture, implementation, and signoff activities for complex SoC/IP programs.

- Define and drive DFT methodologies covering :

1. Scan Architectures

2. JTAG / iJTAG

3. Boundary Scan (BSCAN)

4. ATPG

5. MBIST

- Review and approve DFT plans, test architectures, and coverage targets.

- Develop scalable and efficient DFT solutions aligned with project requirements.

DFT Execution & Signoff :

- Drive ATPG, MBIST, DFT verification, and signoff flows.

- Ensure high test coverage, test quality, and robust validation methodologies.

- Lead silicon bring-up, debug, and yield improvement activities from a DFT perspective.

- Analyze coverage reports and drive closure of DFT-related issues.

Leadership & Team Management :

- Lead, mentor, and guide DFT engineering teams.

- Conduct technical reviews and provide architectural guidance.

- Drive project planning, task allocation, and milestone tracking.

- Manage project risks and ensure timely delivery of DFT objectives.

Cross-Functional Collaboration :

- Collaborate closely with Design, Physical Design, Validation, Product Engineering, and Program Management teams.

- Participate in design reviews and DFT reviews across project phases.

- Communicate project status, risks, and mitigation plans to stakeholders and leadership.

- Support customer interactions and technical discussions where required.

Required Technical Skills :

DFT Expertise :

- Strong hands-on experience in :

1. JTAG / iJTAG / Boundary Scan (BSCAN)

2. Scan Architectures

a. Full Scan

b. Scan Compression

c. Hierarchical DFT

3. ATPG

4. Stuck-at Testing

5. Transition Fault Testing

6. At-Speed Testing

7. MBIST and Memory Test Architectures

8. DFT Verification and Simulation

a. RTL Level

b. Gate-Level

9. SoC Test Architecture

10. Coverage Analysis and Signoff Methodologies

Tools :

Experience with industry-standard DFT tool suites such as :

1. Synopsys

2. Cadence

3. Siemens EDA

4. Equivalent DFT and ATPG tools

Leadership Expectations :

Proven experience as :

1. DFT Technical Lead

2. Lead DFT Engineer

3. DFT Manager

Strong capabilities in :

1. Technical mentoring and team leadership

2. DFT signoff ownership

3. Multi-project planning and execution

4. Stakeholder and cross-functional management

5. Driving technical decisions and resolving complex DFT challenges.

Preferred Candidate Profile :

- Strong technical leadership and ownership mindset.

- Excellent analytical and problem-solving skills.

- Ability to manage multiple priorities in fast-paced semiconductor environments.

- Strong communication and stakeholder management skills.

- Passion for delivering high-quality silicon products.