DFT Staff Engineer

Total Positions: 10

Exp range: 08 - 12 Yrs

Location: Bangalore & Hyderabad

Notice Period: Immediate

Skill:

DFT (Design for Test) is a specialized domain in the semiconductor/VLSI industry that ensures integrated circuits (ASICs/SoCs) are testable during manufacturing. DFT engineers design and implement test structures such as Scan, ATPG, MBIST, LBIST, and JTAG to improve chip quality, fault coverage, and manufacturing yield.

Key skills to target:

- End-to-end DFT implementation

- Scan insertion & compression, ATPG

- MBIST, LBIST, JTAG/Boundary Scan

- DFT signoff, fault coverage, debugging

- RTL, SoC design flow, STA

Tools: Siemens Tessent, Synopsys TestMAX, Cadence Modus

Scripting: TCL, Python, Perl

A DFT Staff Engineer is responsible for designing, implementing, and signing off Design-for-Test (DFT) architecture for complex SoCs/IPs. The role ensures that semiconductor designs are testable, high-quality, and manufacturable, while balancing coverage, performance, power, and cost.

Key Responsibilities:

DFT Architecture & Strategy:

- Define and implement DFT architecture at block/IP or SoC level

- Specify test methodologies (scan, MBIST, boundary scan, compression)

- Ensure testability built early into RTL design flow

- Balance trade-offs between coverage, area, power, and test time

DFT Implementation:

- Scan insertion and stitching

- ATPG pattern generation and simulation

- MBIST / LBIST / boundary scan integration

- Develop and validate DFT timing constraints (STA)

- Execute DFT flows at RTL and gate level

Test Coverage & Quality :

- Analyze and improve fault coverage

- Debug scan/ATPG issues and resolve coverage holes

Optimize :

- Pattern count, test cost, and test time

Verification & Signoff :

- Run DFT verification and DRC checks

- Ensure clean DFT signoff (coverage, timing, power impact)

- Validate patterns using simulation and test tools

- Support DFT integration guidelines at SoC level

Cross-Functional Collaboration :

- Work with RTL design, Physical design (PD), Verification, and Test engineering / ATE teams

- Drive issue resolution across teams

- Ensure end-to-end execution of DFT flows

Silicon Bring-up & Debug :

- Support post-silicon debug and yield improvement

- Debug tester failures and improve manufacturing coverage

- Assist customer or product teams during bring-up

Qualifications :

- BSEE/MSEE (or equivalent)

- Typically 7+ years of DFT / ASIC experience (Staff-level expectation)

- Proven experience in end-to-end DFT implementation and debugging