Description :

Location - Bengaluru.

Exp -12+ Years.

About the Role :

We are seeking a visionary Full Chip Physical Design Architect to lead the architecture and execution of complex SoC physical design flows.

As a Full Chip Physical Design Architect, you will define methodologies, drive innovation, and ensure successful tape-outs of cutting-edge silicon.

This is a high-impact role that requires deep technical expertise, strategic thinking, and the ability to influence global engineering teams.

Responsibilities :

Architecture & Strategy :

- Define full-chip physical design methodologies, flows, and best practices across advanced technology nodes.

- Architect scalable solutions for floorplanning, partitioning, hierarchical design, and integration.

- Drive innovation in automation, design closure strategies, and cross-domain optimizations.

Technical Leadership :

- Own end-to-end chip-level physical design including synthesis, place & route, timing closure, power optimization, and sign-off.

- Lead design reviews, ensuring designs meet stringent performance, power, and area (PPA) targets.

- Collaborate with RTL, verification, DFT, and packaging teams to deliver manufacturable designs.

Execution Excellence :

- Guide teams through timing, power, and signal integrity closure at full-chip scale.

- Partner with EDA vendors to evaluate and deploy next-generation tools and methodologies.

- Ensure successful tape-outs and silicon bring-up for complex SoCs.

Mentorship & Influence :

- Mentor engineers and managers, fostering a culture of technical excellence and innovation.

- Represent the physical design organization in global forums, influencing design strategy across geographies.

Basic Qualifications :

- Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field.

- 12+ years of experience in SoC physical design, with significant expertise at full-chip level.

- Proven track record of delivering multiple tape-outs in advanced nodes (7nm, 5nm, or below).

- Deep expertise in industry-standard EDA tools (Synopsys, Cadence, Mentor).

- Strong background in STA, power analysis, IR drop, electromigration, and physical verification.

- Excellent communication, leadership, and problem-solving skills.

Preferred Qualifications :

- Experience architecting flows for large-scale, hierarchical SoCs.

- Exposure to high-performance CPU/GPU/AI accelerator designs.

- Strong scripting skills (Tcl, Python, Perl) for automation and methodology development.

- Ability to thrive in fast-paced, ambiguous environments and drive clarity across teams.