Lead DFT Engineer / DFT Manager | Bangalore

Location : Bangalore, India

Experience : 10 - 18 Years

Compensation : Best in the Industry

Join Us as a Lead DFT Engineer / DFT Manager!

Are you a highly experienced DFT professional passionate about driving end-to-end DFT strategy and execution for cutting-edge SoCs/IPs?

We are looking for a strong technical leader who can combine deep hands-on DFT expertise with leadership, ownership, and cross-functional collaboration to deliver high-quality silicon solutions.

If you thrive in complex semiconductor environments and enjoy mentoring teams while solving challenging DFT problems, wed love to hear from you.

Key Responsibilities :

DFT Architecture & Strategy :

- Lead end-to-end DFT architecture, implementation, and signoff for complex SoC/IP programs

- Define and drive DFT strategy covering :

1. Scan architectures

2. JTAG / iJTAG

3. BSCAN

4. ATPG

5. MBIST

- Review and approve DFT plans, test architectures, and coverage targets.

Execution & Signoff :

- Drive ATPG, MBIST, and DFT simulation flows with strong signoff ownership

- Lead silicon bring-up, debug, and yield improvement activities from a DFT perspective

- Ensure high test coverage, test quality, and robust validation methodologies.

Leadership & Team Management :

- Lead, mentor, and guide a team of DFT engineers

- Own technical reviews, task planning, and delivery milestones

- Drive schedule management, risk mitigation, and execution excellence across projects.

Cross-Functional Collaboration :

- Work closely with Design, PD, Validation, Product, and Program teams

- Conduct design and DFT reviews with internal and external stakeholders

- Interface with customers and management on DFT status, risks, and execution plans.

Required Technical Expertise :

- Strong hands-on experience in :

1. JTAG / iJTAG / BSCAN

2. Scan Architectures (Full Scan, Compression, Hierarchical DFT)

3. ATPG (Stuck-at, Transition, At-Speed Testing)

4. MBIST & Memory Test Strategies

5. DFT Simulation & Debug (RTL and Gate-Level)

6. SoC Test Architecture & Coverage Analysis.

- Experience with industry-standard DFT tools :

1. Synopsys

2. Cadence

3. Siemens

4. Or equivalent tool suites

Leadership Expectations :

We are looking for professionals with proven experience as :

1. Team Lead

2. Technical Lead

3. DFT Manager

- Hands-on experience in :

1. Team mentoring & technical leadership

2. DFT signoff ownership

3. Multi-project planning & execution

4. Stakeholder management & cross-functional coordination

- Driving technical decisions and resolving complex DFT challenges.

Good to Have :

- Low-Power DFT expertise

- IJTAG network implementation

- Advanced test compression techniques

- Experience handling large/complex SoCs

- Customer-facing or program leadership exposure

Education : B.Tech / M.Tech in Electronics, VLSI, or related field