Role & Responsibilities :

As a Senior FPGA/SoC Functional Safety Architect at HCLTech, you will play a pivotal role in the design, implementation, and integration of FPGA and SoC architectures with a focus on functional safety. You will be responsible for ensuring compliance with industry safety standards, conducting in-depth safety analyses, and driving the development of safety mechanisms for hardware and silicon solutions.

Detailed Responsibilities :

- Lead the architecture design, implementation, and integration of FPGA or SoC systems, ensuring adherence to functional safety standards (ISO 26262).

- Develop and review ARM/RISC-V processor subsystems and associated protocols such as AXI, APB, and Network-on-Chip (NoC).

- Execute comprehensive safety analyses at both IP and full chip levels, including FMEA and FMEDA.

- Define and document safety requirements, technical safety concepts (TSC), and safety mechanisms in alignment with ISO 26262.

- Utilize EDA tools (e.g., Synopsys, Siemens Mentor) for design-level safety analysis and verification.

- Apply and validate fault injection simulation concepts to support functional safety signoff processes.

- Establish and maintain traceability using tools like JAMA or DOORS to ensure complete coverage of safety requirements.

- Oversee the preparation and signoff of functional safety (FUSA) work products and the development of safety manuals.

- Conduct detailed design analysis and ensure I3 conformance review, particularly for ASIL-D level projects.

- Independently manage and support FUSA audits and assessments for both IP and full chip levels.

- Defend process gaps and work product reviews during customer stakeholder engagements.

- Collaborate with customers to identify and implement process improvements.

- Mentor and guide team members, driving effective stakeholder management and communication.

Skill Requirements :

- 12+ years of experience in FPGA or SoC architecture design, implementation, and integration.

- Extensive hands-on experience with ARM/RISC-V processor subsystems and AXI/APB protocol/NOC.

- Deep expertise in functional safety for hardware and silicon, specifically ISO 26262.

- Proven ability to perform safety analysis (IP/full chip), FMEA, and FMEDA.

- Proficient in defining technical safety requirements, concepts, and mechanisms.

- Strong experience with EDA tools for safety analysis (e.g., Synopsys, Siemens Mentor).

- Thorough understanding of fault injection simulation and signoff processes.

- Demonstrated expertise in using traceability tools (JAMA, DOORS).

- Experience in preparing and signing off on FUSA work products and developing safety manuals.

- Ability to independently conduct detailed design analysis, I3 conformance reviews, and handle FUSA audits and assessments (ASIL-D).

- Excellent oral and written communication skills.

- Proven leadership in team and stakeholder management.