Job Title : Hardware Design Engineer 3 - Physical Design (PnR)

Location : Hyderabad

Experience : 5 to 7 Years

Job Summary :

We are seeking an experienced Physical Design Engineer to support the Flow and Methodology team in advanced-node semiconductor design implementation. The ideal candidate will have strong expertise in Place & Route (PnR) methodologies, flow qualification, and design execution across leading-edge technology nodes. This role involves supporting and optimizing PnR workflows for advanced TSMC technologies, enabling efficient design closure and methodology deployment.

Key Responsibilities :

- Support Place & Route workflows for advanced technology nodes including 6nm, 3nm, and 2nm designs.

- Qualify and deploy new EDA tool versions, methodologies, and workflow enhancements.

- Evaluate, benchmark, and validate new tool capabilities and flow improvements.

- Execute and support multiple PnR design blocks for benchmarking, performance evaluation, and methodology validation.

- Drive PPA (Power, Performance, Area) optimization and correlate implementation results with signoff metrics.

- Collaborate with design, methodology, and CAD teams to improve design convergence and productivity.

- Support correlation and closure activities involving STA, EMIR, Physical Verification, and signoff flows.

- Develop and maintain automation scripts to improve workflow efficiency and scalability.

- Troubleshoot implementation issues and provide technical support for physical design execution teams.

Required Skills :

- 6+ years of experience in Physical Design and Place & Route implementation.

- Strong hands-on expertise with :

1. Synopsys Fusion Compiler

2. Cadence Innovus

3. Cadence Cerebrus

- Solid understanding of advanced-node implementation methodologies and design closure techniques.

- Experience with synthesis, Place & Route, STA, and physical verification flows.

- Strong knowledge of low-power design methodologies and implementation flows.

- Proficiency in scripting and automation using :

1. TCL

2. Perl

3. Python

- Experience with PPA optimization, design correlation, and signoff methodologies.

- Familiarity with EMIR analysis and signoff validation processes.

- Strong debugging, analytical, and problem-solving skills.

Preferred Qualifications :

- Experience working on advanced TSMC technology nodes (6nm, 3nm, and/or 2nm).

- Exposure to flow development, methodology enablement, and CAD support activities.

- Experience supporting large-scale SoC implementation projects.

Educational Qualifications :

- B.E./B.Tech./M.E./M.Tech in Electronics, Electrical Engineering, Computer Engineering, or a related field.

Notes :

- Candidates must have strong hands-on Physical Design execution experience with Place & Route methodologies.

- Experience supporting Flow and Methodology teams is highly preferred.

- TSMC 3nm and/or 2nm node experience is mandatory.

- Valid TSMC NDA clearance for 3nm and 2nm technologies is required.