WE ARE HIRING | Hardware Design Engineer II

Bangalore

Experience : 3 to 6 Years

We are looking for a Hardware Design Engineer II with strong expertise in STA concepts and timing constraint management.

Job Duties :

- Must have solid understanding of timing constraints and their verification at SoC and block level along with good understanding of STA concepts to debug timing constraint issues.

- This role will provide SoC and block level timing constraints development exposure.

- Responsibilities will include promotion of multiple IP timing constraints to SoC level and integrating them into SoC timing constraints.

Experience Required :

- Understanding of STA concepts and Timing constraints as well as VLSI design flow.

- Familiarity with Verilog, timing (.lib), LEF, GDS.

- Familiarity with physical design verification, e.g. DRC and LVS.

- Ability to execute and modify scripts in PERL, Unix shell, Tcl, Python or related language.

Must Have :

- Hands-on timing constraint management for large/SOC-level designs.

- Strong STA concepts, debugging skills, and good communication.

- SOC-level experience preferred; strong subsystem-level experience can be considered.

- Exposure to multiple clocks and modes is important.

Tools :

- PrimeTime, TCM, GCA, Fusion Compiler.

Not Required :

- Power sequencing and reset blocking experience.

Important :

- Priority should be given to candidates with genuine hands-on SOC/subsystem timing-constraint experience rather than candidates with only standard PD-flow exposure.