Job Title: FPGA RTL Design Engineer

- Location: Hyderabad, India

- Experience: 5 to 8 Years

- Employment Type: Full-Time

Job Summary:

We are seeking a talented FPGA RTL Design Engineer to join our hardware design team in Hyderabad.

The ideal candidate will be responsible for FPGA-based digital design, RTL development, verification support, synthesis, timing closure, and FPGA bring-up activities for high-performance networking, communication, storage, or SoC-based applications.

Required Skills:

- Strong experience in RTL design using Verilog/SystemVerilog.

- Solid understanding of digital design fundamentals and computer architecture.

- Experience with FPGA development flows from RTL to bitstream generation.

Hands-on experience with FPGA families from:

- AMD (Xilinx UltraScale)

- Intel

Experience with high-speed interfaces such as:

- PCIe/ DDR3/DDR4/DDR5 / Ethernet (1G/10G/25G/100G) / AXI/AHB/APB protocols

Strong understanding of:

- CDC/RDC analysis

- Timing constraints and timing closure

- FPGA resource optimization

- Reset and clocking architectures

Experience using simulation and debug tools. Tools & Technologies:

- AMD Vivado Design Suite

- AMD Vitis Platform

- Intel Quartus Prime

Simulation Tools:

- Siemens EDA QuestaSim

- Synopsys VCS

Scripting:

- Tcl

- Python

- Perl

Preferred Qualifications:

- Experience with FPGA prototyping of ASIC/SoC designs.

- Knowledge of DSP, signal processing, networking, or storage protocols.

- Experience with HLS (High-Level Synthesis) methodologies.

- Familiarity with UVM-based verification environments.

- Exposure to embedded processors such as ARM-based FPGA SoCs.

- Experience with hardware debugging tools such as ILA, SignalTap, and protocol analyzers.

Share your updated CV to vagdevi@semi-leaf.com