Element Technologies is an AI and digital transformation company focused on delivering intelligence that drives measurable outcomes for enterprises.

The organization builds autonomous, decision-driven systems using Agentic AI, Generative AI, and Intelligent Document Processing to simplify complexity, optimize decisions, and enhance user experiences.

Its flagship Elevate platform combines GenAI, OCR, and advanced search to power enterprise-grade document intelligence and smart workflow automation.

Element supports clients across Life Sciences, Financial Services, Retail, Media, and Technology with cloud-native engineering, secure data pipelines, and digital advisory services.

The company emphasizes a people-centered culture where technology, passion, and purpose come together to create impactful, scalable solutions.

Role Description:

This is a full-time Senior Design Verification Engineer role based in Bangalore, offered in an onsite work model.

The Senior Design Verification Engineer will be responsible for planning, developing, and executing verification strategies for complex digital designs, including writing and maintaining testbenches, test plans, and coverage models.

The role involves performing both functional and formal verification of RTL blocks and subsystems, analyzing specifications and micro-architecture documents, and collaborating closely with design, architecture, and firmware teams to ensure robust verification closure.

The engineer will debug simulation failures, root-cause functional issues, and drive fixes in partnership with RTL designers, while continuously refining verification methodologies, flows, and scripts for efficiency and quality.

The role also includes mentoring junior engineers, reviewing their verification work, and contributing to best practices that support high-reliability AI and digital transformation solutions.

Responsibilities within team:

- Test bench design and implementation.

- Test & coverage plan definition.

- Constrained random test development.

- Coverage specification & analysis.

- Reference model design and implementation.

- Automation of the regression test suite.

- Collaboration with architects, logic design, and software engineers ( in remote team setup).

- Architecture review.

- Micro-architecture and code reviews.

- Contribution to the methodology adoption in the team.

- Lab debug simulation support.

Desired technical skills:

- Proficiency in Verilog & System Verilog.

- Solid verification skills : planning, problem solving, debug, adversarial testing and random testing.

- Project based work experience with UVM & VMM methodologies.

- Candidate must have experience with architecting the test-plan & test bench.

- Hands on experience with OTN, Ethernet based protocols, PCIe, AXI,I2C,SPI,MDIO & memory controllers etc. will be an added advantage.

- Familiarity with VCS simulation flow, knowledge of coverage & assertions is desirable.

Relevant Experience :

- 7 to 10 years of hands-on experience in functional verification.