Job Title : DFX Verification Engineer ( High Priority )

Experience : 4-10 Years

Location : Bangalore

Job Description :

We are looking for an experienced DFX Verification Engineer with strong expertise in verifying Design-for-Test (DFT) features for complex SoC/ASIC designs. The ideal candidate should have hands-on experience in SystemVerilog/UVM-based verification and a solid understanding of DFT concepts, including Scan, MBIST, JTAG, and ATPG validation.

Key Responsibilities :

- Develop and execute verification plans for DFx features including Scan, MBIST/LBIST, Boundary Scan (JTAG), memory repair, and low-power test scenarios.

- Create and maintain SystemVerilog/UVM testbenches for DFx validation.

- Verify scan chain integrity, test mode functionality, ATPG pattern validation, and BIST controller functionality.

- Debug verification issues and ensure functional coverage for DFT features.

- Collaborate with Design, DFT, and Physical Design teams to achieve verification closure.

Required Skills :

- Strong understanding of DFT concepts : Scan, ATPG, MBIST/LBIST, and JTAG.

- Hands-on experience with SystemVerilog and UVM.

- Experience with simulation tools such as Synopsys VCS, Cadence Xcelium, or Siemens Questa.

- Familiarity with ATPG tools like TetraMAX, Modus, or FastScan.

- Experience using debug tools such as Verdi or DVE.

- Good knowledge of low-power verification (UPF/CPF), clocking, reset strategies, and digital design fundamentals.

Preferred : Experience in SoC/ASIC verification with strong debugging and verification closure skills.