About the Role :

We are looking for an experienced DFT Engineer to work on complex ASIC/SoC designs. The ideal candidate will have strong expertise in DFT architecture, scan implementation, ATPG, MBIST, IJTAG, and post-silicon validation.

Key Responsibilities :

- Perform RTL and netlist DFT insertion for ASIC/SoC designs.

- Implement and validate SSN, IJTAG (IEEE 1687), MBIST, memory repair, LBIST, and EDT-based scan compression.

- Execute gate-level scan stitching, DRC checks, and ATPG pattern generation for stuck-at and transition fault models.

- Perform Gate-Level Simulations (GLS), analyse test coverage, debug failures, and optimise test patterns.

- Support post-silicon bring-up, ATE validation, and silicon debug.

- Collaborate with cross-functional engineering teams throughout the design and verification lifecycle.

Required Skills :

- 8 - 15 years of experience in Design for Test (DFT) for ASIC/SoC development.

- Strong understanding of DFT methodologies and semiconductor design flow.

- Hands-on experience with scan architecture, ATPG, MBIST, IJTAG, LBIST, scan compression, scan stitching, DRC, and GLS.

- Experience with industry-standard DFT tools such as Tessent, Synopsys Test MAX, Cadence Modus, or equivalent.

- Strong debugging, analytical, and problem-solving skills.

- Good communication and collaboration skills.