Job Description :

Position : DFT Engineer (Design for Test)

Experience : 5-8 Years

Location : Bangalore / Noida

Notice Period : Immediate to 60 Days

Job Summary :

We are looking for an experienced DFT (Design for Test) Engineer with 5-8 years of experience in ASIC/SoC design and DFT implementation. The ideal candidate should have strong expertise in scan insertion, ATPG, MBIST, JTAG, and DFT verification. The role involves collaborating with design, verification, and physical design teams to ensure high test coverage and manufacturability of semiconductor products.

Key Responsibilities :

- Define and implement DFT architecture for complex ASIC/SoC designs.

- Perform scan insertion, scan stitching, and DFT logic integration.

- Generate and validate ATPG patterns to achieve high fault coverage.

- Implement and verify MBIST, LBIST, and JTAG (IEEE 1149.1/1149.6) solutions.

- Analyze test coverage and improve DFT quality metrics.

- Debug DFT-related issues during simulation, synthesis, and silicon bring-up.

- Collaborate with RTL, Verification, Physical Design, and Test Engineering teams.

- Ensure DFT implementation meets quality, timing, and power requirements.

- Support post-silicon validation and production testing.

Required Skills :

- 5-8 years of experience in DFT/ASIC/SoC Design.

- Strong knowledge of :

1. Scan Architecture

2. Scan Insertion & Scan Compression

3. ATPG

4. MBIST/LBIST

5. Boundary Scan (JTAG)

- Hands-on experience with DFT EDA tools such as :

1. Siemens Tessent

2. Synopsys DFT Compiler

3. Synopsys TestMAX

4. Cadence Modus

- Strong understanding of digital design fundamentals.

- Experience with Verilog/SystemVerilog.

- Knowledge of scripting using Tcl, Perl, Python, or Shell.

- Familiarity with Linux/Unix environments.

- Good understanding of STA and synthesis flow.

- Experience in debugging DFT issues and improving fault coverage.

Preferred Skills :

- Experience with advanced semiconductor process nodes (16nm/7nm/5nm or below).

- Exposure to low-power design methodologies (UPF/CPF).

- Knowledge of SoC integration and physical design flow.

- Experience with production test and silicon bring-up.

- Familiarity with CI/CD and automation scripting.

Qualifications :

- Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Computer Engineering, or a related field.

Work Location :

- Bangalore / Noida

Notice Period :

- Immediate to 60 Days preferred.

- Share the resume on rakhi.ankush@talentcorner.in