Job Title: DFT Engineer (MBIST) | Scan | IJTAG | Tessent | ASIC/SoC

Experience: 5-10 Yrs

Job Location: Bengaluru | Visakhapatnam (Vizag) | Kochi | Ahmedabad

Employment Type: Full-Time

Job Summary:

We are looking for experienced DFT Engineers with strong expertise in MBIST (Memory Built-In Self-Test), Scan DFT, and Tessent DFT flows for complex ASIC/SoC designs. The ideal candidate should have hands-on experience in DFT architecture, scan and MBIST insertion, ATPG, timing closure, IJTAG, and post-silicon validation. You will collaborate with Design, Physical Design, STA, and Validation teams to deliver high-quality, testable silicon while ensuring robust DFT implementation and sign off.

Key Responsibilities:

- Implement and validate Top-Level and Block-Level DFT architectures for ASIC/SoC designs.

- Execute Flat and Hierarchical DFT insertion methodologies.

- Perform Scan insertion, MBIST insertion, ATPG pattern generation, and verification at full-chip level.

- Develop and validate DFT constraints to achieve timing closure in DFT modes.

- Analyze and resolve timing issues related to scan shift, capture, and MBIST operations.

- Work with IJTAG (IEEE 1687), JTAG (IEEE 1149), TAP, ICL, and PDL for DFT implementation and debug.

- Generate and optimize STIL test patterns for improved test coverage, throughput, and reduced test time.

- Support RTL analysis, logic synthesis, physical design, STA, Formality, and simulation activities from a DFT perspective.

- Debug DFT issues during Pre-Silicon and post-silicon validation.

- Collaborate with cross-functional teams including Design, Physical Design, STA, Validation, and Product Engineering.

- Mentor junior engineers and contribute to technical reviews and knowledge-sharing sessions.

Required Skills:

- 510 years of experience in ASIC/SoC DFT implementation.

- Strong expertise in MBIST methodologies and implementation.

- Experience in Top-Level and Block-Level DFT.

- Hands-on experience with Flat and Hierarchical DFT insertion flows.

- Experience in Scan insertion, MBIST insertion, ATPG pattern generation, and verification.

- Good understanding of Memory fault models and memory test algorithms.

- Expertise in IJTAG (IEEE 1687) and JTAG (IEEE 1149).

- Experience with ICL extraction, ICL debugging, correction, and PDL programming using Tessent.

- Strong knowledge of STIL test generation and optimization.

- Experience in DFT timing closure, including scan shift, capture timing, and MBIST constraints.

- Ability to generate and validate DFT timing constraints for high-speed designs.

- Good understanding of RTL analysis, Logic Synthesis, Physical Design, STA, Formality, and Simulation.

Preferred Skills:

- Experience with Tessent DFT Suite.

- Familiarity with Intel Mastic flows.

- Exposure to testing Analog and Mixed-Signal IPs such as PLLs, MIPI, and related interfaces.

- Experience in Post-Silicon Bring-up, diagnosis, and failure analysis.

- Understanding of Power Estimation and Power Management for DFT modes.

- Knowledge of Deep Sub-Micron design challenges and DFT implications.

- Strong debugging, analytical, and problem-solving skills.

- Excellent communication and stakeholder management skills.

- Experience mentoring junior engineers.

Education:

B.E./B.Tech/M.E./M.Tech in Electrical Engineering, Electronics & Communication, VLSI, or a related discipline.