Job Description :

Immediate Joiners or less than 30 days notice period.

We are looking for a skilled DFT Engineer with a strong understanding of boundary scan, MBIST, scan insertion, ATPG and simulation concepts. The role involves SoC-level DFT implementation, verification, debugging, timing coordination and support for silicon bring-up and production activities.

Key Responsibilities :

- Perform SoC-level DFT implementation and verification activities.

- Work on MBIST insertion, scan insertion, ATPG pattern generation and related simulations.

- Execute MBIST, boundary-scan and scan-pattern simulations using industry-standard DFT tools.

- Handle OCC/OPCG insertion, EDT/compression logic insertion and scan-clock modules.

- Perform zero-delay and SDF timing simulations and debug simulation failures.

- Improve scan test coverage using appropriate fault models and coverage-improvement techniques.

- Provide test-mode timing constraints and work closely with STA and Physical Design teams.

- Support post-silicon bring-up and production activities, including tester debugging using Shmoo plots and graphs.

- Collaborate with customer-facing and cross-functional teams and mentor DFT Engineers when required.

Required Skills :

- Clear understanding of BSCAN, MBIST, scan, ATPG and simulation concepts.

- Hands-on experience in at least one area: MBIST insertion, scan insertion, ATPG pattern generation/simulation, or MBIST/BSCAN simulation.

- Experience with DFT tools from Cadence, Siemens Tessent or Synopsys.

- Strong debugging skills using GUI mode in simulators such as VCS, NCSim or Xcelium.

- SoC-level DFT experience covering OCC/OPCG, EDT/compression logic and scan-clock handling.

- Experience providing test-mode timing constraints to STA and Physical Design teams.

- Strong communication, problem-solving and cross-functional coordination skills.

Preferred Skills :

- Experience with both zero-delay and SDF timing simulations.

- Knowledge of stuck-at, Transition Delay Fault (TDF) and IDDQ fault models.

- Experience with scan test-coverage improvement techniques.

- Exposure to post-silicon bring-up, production testing and tester-level debugging.

- Experience leading or mentoring DFT Engineers.