Job Description :

Requirements :

- 4 to 10 years of hands-on experience in DFT methodologies, with expertise in Scan & ATPG, MBIST.

- Strong knowledge of DFT tools such as Synopsys, Mentor Graphics, or Cadence.

- Experience in fault modeling, pattern generation, and coverage analysis.

- Proficiency in scripting (TCL, Python, Perl, or Shell) for automation.

- Excellent problem-solving skills and ability to work in a fast-paced environment.

Job Responsibilities :

- Implement and validate DFT architectures for complex SoCs.

- Perform scan insertion and ensure proper integration into the design.

- Develop and optimize ATPG patterns to achieve high fault coverage.

- Work closely with RTL, verification, and physical design teams to resolve DFT-related issues.

- Support post-silicon bring-up, debug, and ATE (Automated Test Equipment) testing.

- Ability to work in an international team, dynamic environment.

- Ability to learn and adapt to new tools and methodologies.

- Ability to do multi-tasking & work on several high priority designs in parallel.

- Excellent problem solving skills.

- Excellent communication and team work skills and good English is required.