Design Verification Engineer - UVM/System Verilog

Job Description:

- M.Tech/B.Tech in Electronics and Communication Engineering or related field.

- Proficiency in Verilog, System Verilog and UVM methodology.

- Ability to develop VIPs.

- Write test plans based on the feature list.

- Strong understanding of Digital Design Concepts, SoC Architecture, Processor architecture.

- Ability to debug test failures, excellent problem solving skills.

- Scripting (Perl, Python) for test automation.

- Familiarity with Simulation environment (Synopsys, Cadence).

- Knowledge on Assertion based Verification.

- Knowledge on SystemC modelling is a plus.

- Knowledge of AMBA protocols.

- Knowledge of the C programming language is a plus.

Key Skills:

- Verilog, System Verilog, UVM

- Digital Design, SoC Architecture, Processor Architecture

- AMBA Protocols

- Scripting (Perl, Python)

- Simulation Tools (Synopsys, Cadence)

Bonus Skills:

- SystemC, PCIe/CXL/DDR/USB, C programming