Position : Design Verification role for IP development team.

Experience : B. Tech/M.Tech with 8+ years of relevant experience.

Location :

Position is based in Bangalore/Noida, part of Cadence IP Group - Preferred location is Bangalore.

Job Description :

Responsibilities :

- Verification role for Serial and Interface Design IPs verification (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C).

- UVM testbench development to build a robust, scalable and efficient testbench to verify the design IPs.

- In addition to UVM functional verification, role could involve Formal verification of complex design modules.

- In addition to UVM functional verification, role could involve participating in Emulation qualification of design IPs.

- Architect and implement robust UVM-based testbenches from scratch to verify complex PCIe controller features, ensuring full compliance with industry specifications.

- Drive the development of constrained-random verification environments to identify corner-case bugs, thereby reducing the risk of silicon re-spins.

- Collaborate with RTL designers to debug complex protocol-level issues, ensuring rapid resolution and adherence to aggressive project timelines.

- Understand design and produce detailed verification strategy and test plan.

- Self-starter and learner with passion for getting the job done on time with great quality.

- Strong problem solving, analytical and debug skills.

- Excellent verbal and written communications skills.

- Clearly communicate project status, issues etc.

Behavioral Skills :

- Must possess strong written, verbal and presentation skills.

- Good communication and interpersonal skills, demonstrate teamwork and collaboration skills.

- Ability to establish a close working relationship with both customer peers and management.

- Explore whats possible to get the job done, including creative use of unconventional solutions.

- Work effectively across functions and geographies.

- Push to raise the bar while always operating with integrity.