Design Engineer - RTL/System Verilog

Role : Design Engineer I3C

Location : Noida/Bengaluru

Experience : 5+ Years

Employment Type : 1-Year Contract

Role & Responsibilities :

- Understand customer-specific wrapper-level implementations of the I3C module.

- Debug and resolve design and integration issues.

- Execute design tool flows and troubleshoot failures.

- Update block-level and integration documentation.

- Work on Autonomous I3C Target and Advanced I3C Target with APB wrappers.

Required Skills :

- Strong knowledge of I3C protocol and RTL design.

- Hands-on experience with Verilog and SystemVerilog.

- Understanding of APB interface and IP integration.

- Experience in wrapper-level debugging and block integration.

- Strong analytical and problem-solving skills.

Preferred Candidate Profile :

- Candidates with 5+ years of relevant semiconductor design experience and hands-on exposure to I3C IP wrappers, RTL debugging, APB interfaces, and integration flows are preferred.