Job Description :

We are looking for a highly experienced Lead / Principal DFT Engineer with 10+ years of hands-on expertise in Design-for-Testability (DFT) architecture, implementation, and verification. In this role, you will lead end-to-end DFT strategies across high-complexity cores and SoCs.

You will be responsible for defining scan architectures, implementing advanced compression techniques, driving MBIST integration, and executing pattern generation, timing/non-timing simulations, and fault coverage optimization.

Key Responsibilities :

DFT Architecture & Implementation :

- Architecture & Planning : Define and architect comprehensive DFT strategies at both the core and full SoC levels for multi-million gate designs.

- Scan & Compression : Drive scan insertion, boundary scan, and advanced scan compression architectures (e.g., EDP, EDT) to minimize test time and silicon test cost.

- Advanced Architectures : Implement and optimize Streaming Scan Network (SSN) architectures to improve packetized test data transport efficiency across complex SoCs.

- Clocking & OCC : Design and integrate On-Chip Clock (OCC) logic for at-speed test, working closely with clock architecture teams to handle internal, functional, and test clock domains safely.

Memory-BIST (MBIST) & Analog Integration :

- Architect, insert, and verify Memory-BIST (MBIST) logic across various memory arrays (SRAM, ROM, multi-port memories), including repair and diagnostic features.

- Integrate IEEE 1149.1 / 1149.6 (Boundary Scan) and IEEE 1687 (IJTAG) infrastructure.

ATPG & Coverage Optimization :

- Lead ATPG pattern generation for Stuck-At, At-Speed (Transition Delay), Path Delay, and Cell-Aware fault models.

- Conduct in-depth fault coverage analysis, identify coverage gaps, and implement testability enhancements (e.g., test point insertion) to meet target DPM (Defects Per Million) goals.

Verification & Simulation :

- Execute and debug timing (SDF annotated) and non-timing gate-level simulations (GLS) for all test modes (Scan, MBIST, Boundary Scan, At-Speed).

- Resolve timing violations, race conditions, and X-bounding issues in test modes.

Cross-Functional Collaboration & Handoff :

- Work closely with Physical Design, Synthesis, STA, and Analog IP teams to ensure clean DFT timing closure and minimal area/power overhead.

- Deliver complete ATPG pattern packages (WGL, STIL) to ATE/Product Engineering teams and assist with silicon bring-up and pattern debug on automated test equipment.

Required Skills & Qualifications :

- Experience : 10+ years of dedicated DFT experience on complex, multi-million gate SoCs in deep sub-micron technology nodes (7nm, 5nm, 3nm, or similar).

- Scan & ATPG Expertise : Extensive hands-on experience in scan insertion, compression methodologies, pattern generation, and coverage debugging.

- Tool Mastery : Hands-on experience with industry-standard EDA tools (e.g., Siemens EDA Tessent tool suite, Synopsys DFTMAX / Tetramax, or Cadence Modus).

- Architecture Knowledge : Strong understanding of SSN (Streaming Scan Network) architecture, Clocking architectures/OCC, and Memory-BIST (MBIST) insertion.

- Simulation Skills : Proven expertise in running, debugging, and resolving failures in both non-timing and SDF-annotated timing simulations (GLS).

- Scripting : Proficiency in Tcl, Perl, or Python for test automation and tool flows.

- Communication : Excellent verbal and written communication skills to collaborate across global cross-functional teams.

Preferred Qualifications :

- Prior experience leading DFT technical initiatives or mentoring junior DFT engineers.

- Direct exposure to post-silicon bring-up, silicon debugging, and ATE pattern handoff/troubleshooting.

- Knowledge of Automotive Safety (ISO 26262) DFT/BIST standards or Functional Safety requirements is a plus.