Job Overview :

We are looking for an experienced ASIC STA Engineer with strong hands-on expertise in Static Timing Analysis (STA), pre-layout and post-layout timing analysis, and timing closure. The ideal candidate should have experience working on complex ASIC/SoC designs and timing sign-off, with strong knowledge of SDC constraints, MMMC analysis, setup/hold closure, and PrimeTime and/or Tempus. Experience supporting multiple tape-outs is highly preferred.

Key Responsibilities :

- Perform pre-layout and post-layout STA for ASIC/SoC designs.

- Perform timing analysis and drive timing closure.

- Develop, review, and debug SDC constraints at block and top levels.

- Perform MMMC (Multi-Mode Multi-Corner) analysis in Functional and DFT modes.

- Analyze and resolve setup, hold, clock, timing exception, and PVT corner issues.

- Perform timing sign-off using Synopsys PrimeTime and/or Cadence Tempus.

- Support SDF generation, Gate-Level Simulation (GLS), and ETM/timing model validation.

- Work closely with RTL, Synthesis, Physical Design, DFT, and SoC teams.

- Support timing sign-off and tape-out activities.

Mandatory Skills :

- 6+ years of hands-on ASIC STA experience.

- Strong experience in Static Timing Analysis (STA).

- Strong hands-on experience in Pre-Layout and Post-Layout STA.

- Strong experience in Timing Closure.

- Hands-on experience with MMMC analysis.

- Strong experience developing and debugging SDC / Timing Constraints.

- Strong understanding of Setup and Hold Analysis.

- Experience with Clock Timing and Clock Constraints.

- Understanding of Timing Exceptions and PVT Corners.

- Hands-on experience with PrimeTime and/or Tempus.

- Experience supporting ASIC/SoC timing sign-off.

- Experience with multiple tape-outs.

Good to Have :

- Experience with SDF generation.

- Experience supporting Gate-Level Simulation (GLS).

- Experience with ETM / Timing Model Validation.

- Good understanding of Synthesis.

- Understanding of DFT.

- Exposure to LEC, Lint, and CDC.

- Experience working with RTL, Physical Design, and SoC teams.