Description :

- Perform end-to-end physical design activities for ASIC/SoC projects

- Work on floorplanning, placement, CTS, routing, timing closure, and physical verification

- Conduct timing analysis, signal integrity checks, and power optimization

- Handle advanced technology nodes such as 16nm and 5nm

- Support DFT insertion, low-power methodologies, and multi-clock domain designs

- Perform physical verification and manufacturing sign-off activities

- Collaborate with cross-functional design and verification teams

- Develop and maintain automation scripts for design flow optimization

Required Skills & Qualifications :

- 5 to 12 years of experience in ASIC/SoC Physical Design

- Strong expertise with EDA tools such as :

1. Synopsys ICC2 / Fusion Compiler

2. Cadence Innovus

3. PrimeTime

4. Voltus

- Expertise in timing analysis, signal integrity, and power analysis

- Experience with advanced technology nodes (16nm / 5nm preferred)

- Good understanding of DFT insertion and low-power design techniques

- Experience with multi-clock domain handling

- Strong knowledge of physical verification and manufacturing sign-off

- Excellent debugging and problem-solving skills

Preferred Qualifications :

- Experience working on Automotive or Industrial MPU/MCU SoCs

- Familiarity with ISO 26262 and safety-critical design standards

- Knowledge of EM/IR analysis and reliability checks

- Familiarity with scripting languages such as Tcl, Perl, or Python for automation

- Experience handling high-performance SoCs and complex IP blocks